dc.creator | Núñez Martínez, Juan | es |
dc.creator | Avedillo de Juan, María José | es |
dc.creator | Quintana Toledo, José María | es |
dc.date.accessioned | 2024-01-25T12:00:04Z | |
dc.date.available | 2024-01-25T12:00:04Z | |
dc.date.issued | 2013-09 | |
dc.identifier.citation | Núñez Martínez, J., Avedillo de Juan, M.J. y Quintana Toledo, J.M. (2013). Novel pipeline architectures based on Negative Differential Resistance devices. Microelectronics Journal, 44 (9), 807-813. https://doi.org/10.1016/j.mejo.2013.06.012. | |
dc.identifier.issn | 0026-2692 | es |
dc.identifier.uri | https://hdl.handle.net/11441/153994 | |
dc.description.abstract | Devices exhibiting Negative Differential Resistance (NDR) in their I-V characteristic are attractive from the design point of view and circuits exploiting it have been reported showing advantages in terms of performance and/or cost. In particular, logic circuits based on the monostable to bistable operating principle can be built from the operation of two series connected NDR devices with a clocked bias. Monostable to Bistable Logic Element (MOBILE) gates allow compact implementation of complex logic function like threshold gates and are very suitable for the implementation of latch-free fine grained pipelines. This pipelining relies on the self-latching feature of MOBILE operation. Conventionally, MOBILE gates are operated in a gate level pipelined fashion using a four-phase overlapped clock scheme. However other simpler, and higher through-output interconnection schemes are possible. This paper describes latch-free MOBILE pipeline architectures with a single clock and with a two phase clock scheme which strongly rely on distinctive characteristics of the MOBILE operating principle. Both the proposed architectures are analyzed and experimentally validated. The fabricated circuits use a well-known transistor NDR circuit (MOS-NDR) and an efficient MOBILE gate topology built on its basis. Both solutions are compared and their distinctive characteristics with respect to domino based solutions are pointed out. | es |
dc.format | application/pdf | es |
dc.format.extent | 7 p. | es |
dc.language.iso | eng | es |
dc.publisher | Elsevier | es |
dc.relation.ispartof | Microelectronics Journal, 44 (9), 807-813. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Negative differential Resistance (NDR) | es |
dc.subject | Fine-grain pipeline | es |
dc.subject | Monostable to Bi- stable Logic Elements (MOBILE) | es |
dc.subject | MOS-NDR | es |
dc.title | Novel pipeline architectures based on Negative Differential Resistance devices | es |
dc.type | info:eu-repo/semantics/article | es |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | TEC2010-18937 | es |
dc.relation.projectID | TEC2011-28302 | es |
dc.relation.publisherversion | https://www.sciencedirect.com/science/article/pii/S0026269213001493 | es |
dc.identifier.doi | 10.1016/j.mejo.2013.06.012 | es |
dc.journaltitle | Microelectronics Journal | es |
dc.publication.volumen | 44 | es |
dc.publication.issue | 9 | es |
dc.publication.initialPage | 807 | es |
dc.publication.endPage | 813 | es |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España | es |
dc.contributor.funder | European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER) | es |