Ponencia
Static Linearity BIST for Vcm-based Switching SAR ADCs Using a Reduced-code Measurement Technique
Autor/es | Feitoza, Renato S.
Barragan, Manuel J. Ginés Arteaga, Antonio José Mir, Salvador |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2020 |
Fecha de depósito | 2023-05-31 |
Publicado en |
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ISBN/ISSN | 978-172817044-2 |
Resumen | This work presents a reduced-code strategy for the static linearity self-testing of Vcm -based successive-approximation analog to digital converters (SAR ADCs). These techniques take advantage of the repetitive operation ... This work presents a reduced-code strategy for the static linearity self-testing of Vcm -based successive-approximation analog to digital converters (SAR ADCs). These techniques take advantage of the repetitive operation of SAR ADCs for reducing the number of necessary measurements for static linearity testing. In this paper we discuss the application of these techniques for the Vcm-based SAR ADC topology and present a practical BIST implementation based on an embedded incremental ADC. Electrical simulation results at transistor level are presented to validate the feasibility of the proposed on-chip reduced-code static linearity test. |
Cita | Feitoza, R.S., Barragan, M.J., Ginés Arteaga, A.J. y Mir, S. (2020). Static Linearity BIST for Vcm-based Switching SAR ADCs Using a Reduced-code Measurement Technique. En International New Circuits and Systems Conference (295-298), Montreal, Canadá: Institute of Electrical and Electronics Engineers (IEEE). |
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