Ponencia
Self-Testing Analog Spiking Neuron Circuit
Autor/es | El-Sayed, Sarah A.
Camuñas Mesa, Luis Alejandro Linares Barranco, Bernabé Stratigopoulos, Haralampos G. |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2019 |
Fecha de depósito | 2023-01-31 |
Publicado en |
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ISBN/ISSN | 978-172811201-5 |
Resumen | Hardware-implemented neural networks are foreseen to play an increasing role in numerous applications. In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. ... Hardware-implemented neural networks are foreseen to play an increasing role in numerous applications. In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. In particular, we propose a self-testable version of a spiking neuron circuit. The self-test wrapper is a compact circuit composed of a low-precision ramp generator and a small digital block. The self-test principle is demonstrated on a spiking neuron circuit design in 0.35μm CMOS technology. |
Cita | El-Sayed, S.A., Camuñas Mesa, L.A., Linares Barranco, B. y Stratigopoulos, H.G. (2019). Self-Testing Analog Spiking Neuron Circuit. En 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (81-84), Lausanne, Suiza: Institute of Electrical and Electronics Engineers. |
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