Ponencia
Design Flow to Evaluate the Performance of Ring Oscillator PUFs on FPGAs
Autor/es | Martínez Rodríguez, Macarena Cristina
Camacho Ruiz, Eros Sánchez Solano, Santiago Brox Jiménez, Piedad |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2021 |
Fecha de depósito | 2023-01-19 |
Publicado en |
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ISBN/ISSN | 9781665421164 2640-5563 2471-6170 |
Resumen | This work presents a unified framework to design, implement and evaluate the performance of Ring Oscillator Physical Unclonable Functions (RO PUFs) on FPGAs. The design flow uses a Digital Signal Processing (DSP) tool ... This work presents a unified framework to design, implement and evaluate the performance of Ring Oscillator Physical Unclonable Functions (RO PUFs) on FPGAs. The design flow uses a Digital Signal Processing (DSP) tool integrated into the Matlab environment. The use of this tool eases the evaluation of the PUF performance. The DSP tool provides an environment to apply the challenges to the RO PUF, acquire the responses by using hardware (HW) co-simulation, and compute a set of metrics to quantify the stability, probability and entropy of the PUF response. Additionally, the robustness of the PUF response is proved in the generation of secret keys. The design flow was applied to evaluate the performance of RO PUFs implemented on 17 Basys 3 Artix-7 FPGA Boards. |
Agencias financiadoras | European Union (UE). H2020 Ministerio de Ciencia e Innovación (MICIN). España Agencia Estatal de Investigación. España Consejo Superior de Investigaciones Científicas (CSIC) |
Identificador del proyecto | H 2020 SPIRS 952622
PID2020-116664RBI00 MCIN/AEI/10.13039/501100011033 LINKA20216 |
Cita | Martínez Rodríguez, M.C., Camacho Ruiz, E., Sánchez Solano, S. y Brox Jiménez, P. (2021). Design Flow to Evaluate the Performance of Ring Oscillator PUFs on FPGAs. En 36th Conference on Design of Circuits and Integrated Systems, DCIS 2021 Vila do Conde, Portugal: Institute of Electrical and Electronics Engineers. IEEE. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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DCIS_2021_OA.pdf | 1.120Mb | [PDF] | Ver/ | |