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dc.creatorJiménez, Manueles
dc.creatorNúñez Martínez, Juanes
dc.creatorAvedillo de Juan, María Josées
dc.date.accessioned2022-07-07T09:53:23Z
dc.date.available2022-07-07T09:53:23Z
dc.date.issued2020
dc.identifier.citationJiménez, M., Núñez Martínez, J. y Avedillo de Juan, M.J. (2020). Hybrid-Phase-Transition FET Devices for Logic Computation. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 6 (1), 9090162.
dc.identifier.issn2329-9231es
dc.identifier.urihttps://hdl.handle.net/11441/135101
dc.description.abstractHybrid-phase-transition FETs (HyperFETs), built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON-to- OFF current ratio. In this article, we describe a comprehensive study carried out to explore the potential of these devices for low-power and energy-limited logic applications. HyperFETs with different ON-OFF current tradeoffs are evaluated at the circuit level. The results show limited improvement over conventional transistors in terms of power and energy. However, based on this analysis, this article proposes different design techniques to overcome the drawbacks identified in the study and thereby make better use of HyperFETs. Hybrid circuits, using both FinFETs and HyperFETs, and circuits combining different HyperFET devices are introduced and evaluated. At some frequencies, reductions of over 40% were obtained with respect to FinFET-only implementations, while minimum energy per operation values were obtained, which were lower than those achieved with low standby power (LSTP) FinFETs and high-performance (HP) FinFETs. This article also evaluates the impact of PTM transition time on the power performance of HyperFET circuits.es
dc.description.sponsorshipMinisterio de Economía y Competitividad, FEDER TEC2017-87052-Pes
dc.formatapplication/pdfes
dc.format.extent8 p.es
dc.language.isoenges
dc.publisherIEEEes
dc.relation.ispartofIEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 6 (1), 9090162.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectDevice-circuit codesignes
dc.subjectHybrid-phase-transition FET (HyperFET)es
dc.subjectLow poweres
dc.subjectPhase transition deviceses
dc.subjectSteep-slope deviceses
dc.titleHybrid-Phase-Transition FET Devices for Logic Computationes
dc.typeinfo:eu-repo/semantics/articlees
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/publishedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.projectIDTEC2017-87052-Pes
dc.relation.publisherversionhttps://dx.doi.org/10.1109/JXCDC.2020.2993313es
dc.identifier.doi10.1109/JXCDC.2020.2993313es
dc.journaltitleIEEE Journal on Exploratory Solid-State Computational Devices and Circuitses
dc.publication.volumen6es
dc.publication.issue1es
dc.publication.initialPage9090162es
dc.contributor.funderMinisterio de Economía y Competitividad (MINECO). Españaes
dc.contributor.funderEuropean Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER)es

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