Article
SW-VHDL Co-Verification Environment Using Open Source Tools
Author/s | Muñoz-Quijada, María
Sanz, Luis Guzmán-Miranda, Hipólito ![]() ![]() ![]() ![]() ![]() ![]() |
Department | Universidad de Sevilla. Departamento de Ingeniería Electrónica |
Publication Date | 2020-12 |
Deposit Date | 2022-03-04 |
Published in |
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Abstract | The verification of complex digital designs often involves the use of expensive simulators.
The present paper proposes an approach to verify a specific family of complex hardware/software
systems, whose hardware part, ... The verification of complex digital designs often involves the use of expensive simulators. The present paper proposes an approach to verify a specific family of complex hardware/software systems, whose hardware part, running on an FPGA, communicates with a software counterpart executed on an external processor, such as a user/operator software running on an external PC. The hardware is described in VHDL and the software may be described in any computer language that can be interpreted or compiled into a (Linux) executable file. The presented approach uses open source tools, avoiding expensive license costs and usage restrictions. |
Funding agencies | European Commission (EC) |
Project ID. | 687220
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Citation | Muñoz-Quijada, M., Sanz, L. y Guzmán-Miranda, H. (2020). SW-VHDL Co-Verification Environment Using Open Source Tools. Electronics, 9 (12), 2104. |
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