Ponencia
FPGA design example for maximum operating frequency measurements
Autor/es | Jiménez Fernández, Carlos Jesús
Parra Fernández, María del Pilar Baena Oliva, María del Carmen Valencia Barrero, Manuel Potestad Ordóñez, Francisco Eugenio |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Fecha de publicación | 2018 |
Fecha de depósito | 2022-01-26 |
Publicado en |
|
ISBN/ISSN | 978-1-5386-0928-6 |
Resumen | The best way to learn how to design digital systems
at the RT level is to use practical examples. In addition, from a
teaching point of view, the more practical they are, the more
attractive to students. But for a design ... The best way to learn how to design digital systems at the RT level is to use practical examples. In addition, from a teaching point of view, the more practical they are, the more attractive to students. But for a design to be attractive, even if it is presented with a low complexity, it is not possible to do it in a single practice session. This paper presents, as a demonstrator, the design at RT level and its implementation in FPGA of a digital system that uses the Trivium flow cipher and on which measurements of maximum operating frequency are made. This circuit is designed in three laboratory sessions of about two hours each. |
Agencias financiadoras | Ministerio de Economía y Competitividad (MINECO). España Consejo Superior de Investigaciones Científicas (CSIC) |
Identificador del proyecto | TEC2013-45523-R
TEC2016-80549-R LACRE CSIC 201550E039 |
Cita | Jiménez Fernández, C.J., Parra Fernández, M.d.P., Baena Oliva, M.d.C., Valencia Barrero, M. y Potestad Ordoñez, F.E. (2018). FPGA design example for maximum operating frequency measurements. En TAEE 2018: XIII Technologies Applied to Electronics Teaching Conference La Laguna, Tenerife: IEEE Computer Society. |
Ficheros | Tamaño | Formato | Ver | Descripción |
---|---|---|---|---|
FPGA_design_example_for_maximu ... | 7.290Mb | [PDF] | Ver/ | |