Ponencias (Instituto de Microelectrónica de Sevilla (IMSE-CNM))

URI permanente para esta colecciónhttps://hdl.handle.net/11441/10971

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Mostrando 1 - 20 de 309

Combining CRYSTALS-Kyber Homomorphic Encryption with Garbled Circuits for Biometric Authentication
(Institute of Electrical and Electronics Engineers, 2024-12-11) Arjona, Rosario; Franco Moreno, Claudia; Román Hajderek, Roberto; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Agencia Estatal de Investigación. España
Biometric data are sensitive according to personal data regulations and ISO/IEC 24745. In a biometric recognition system, biometric data should be protected from their generation to their comparison. In this work, we combine postquantum homomorphic encryption using CRYSTALS-Kyber (the base post-quantum algorithm of the FIPS 203 standard for module-lattice-based key-encapsulation mechanism, recently approved by the NIST) with Garbled Circuits, which allow different parties to compute the result of an operation from private inputs. We propose a protected biometric authentication scheme in which homomorphic encryption with CRYSTALS-Kyber public-key encryption computes the difference between the reference and a query, and a Garbled Circuit (GC) performs the comparison with a threshold. Two GC frameworks, TinyGarble (based on Verilog) and TinyGarble2 (based on C++), are employed to design a privacy-preserving face authentication system with FaceNet embeddings. The two frameworks are compared in terms of design and computation costs. In any case, the authentication takes, approximately, 0.5 seconds.
Hardware Security for eXtended Merkle Signature Scheme Using SRAM-based PUFs and TRNGs
(Institute of Electrical and Electronics Engineers Inc., 2020-12-18) Román Hajderek, Roberto; Arjona, Rosario; Arcenegui Almenara, Javier; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Agencia Estatal de Investigación. España; Junta de Andalucía
Due to the expansion of the Internet of Things (IoT), there is an increasing number of interconnected devices around us. Integrity, authentication and non-repudiation of data exchanged between them is becoming a must. This can be achieved by means of digital signatures. In recent years, the eXtended Merkle Signature Scheme (XMSS) has gained popularity in embedded systems because of its simple implementation, post-quantum security, and minimal security assumptions. From a hardware point of view, the security of digital signatures strongly depends on how the private keys are generated and stored. In this work, we propose the use of SRAMs as True Random Generators (TRNGs) and Physically Unclonable Functions (PUFs) to generate and reconstruct XMSS keys in a trusted way. We achieve a low-cost solution that only adds lightweight operations to the signature itself, such as repetition decoding and XORing, and does not require additional hardware (like secure non-volatile memories) since the manufacturing variations of the SRAM inside the IoT device are exploited. As a proof of concept, the solution was implemented in an IoT board based on the ESP32 microcontroller.
Secure management of IoT devices based on blockchain non-fungible tokens and physical unclonable functions
(Springer Nature, 2020-10) Arcenegui Almenara, Javier; Arjona, Rosario; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Agencia Estatal de Investigación. España; Junta de Andalucía
One of the most extended applications of blockchain technologies for the IoT ecosystem is the traceability of the data and operations generated and performed, respectively, by IoT devices. In this work, we propose a solution for secure management of IoT devices that participate in the blockchain with their own blockchain accounts (BCAs) so that the IoT devices themselves can sign transactions. Any blockchain participant (including IoT devices) can obtain and verify information not only about the actions or data they are taking but also about their manufacturers, managers (owners and approved), and users. Non Fungible Tokens (NFTs) based on the ERC-721 standard are proposed to manage IoT devices as unique and indivisible. The BCA of an IoT device, which is defined as an NFT attribute, is associated with the physical device since the secret seed from which the BCA is generated is not stored anywhere but a Physical Unclonable Function (PUF) inside the hardware of the device reconstructs it. The proposed solution is demonstrated and evaluated with a low-cost IoT device based on a Pycom Wipy 3.0 board, which uses the internal SRAM of the microcontroller ESP-32 as PUF. The operations it performs to reconstruct its BCA in Ethereum and to carry out transactions take a few tens of milliseconds. The smart contract programmed in Solidity and simulated in Remix requires low gas consumption.
A Dual-Factor Access Control System Based on Device and User Intrinsic Identifiers
(IEEE, 2016-12) Arjona, Rosario; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
This paper proposes an access control system based on the simultaneous authentication of what the user has and who the user is. At enrollment phase, the wearable access device (a smart card, key fob, etc.) stores a template that results from the fusion of the intrinsic device identifier and the user biometric identifier. At verification phase, both the device and user identifiers are extracted and matched with the stored template. The device identifier is generated from the start-up values of the SRAM in the device hardware, which are exploited as a Physically Unclonable Function (PUF). Hence, if the device hardware is cloned, the authentic identifier is not generated. The user identifier is obtained from level-1 fingerprint features (directional image and singular points), which are extracted from the fingerprint images captured by the sensor in the access device. Hence, only genuine users with genuine devices are authorized to access and no sensitive information is stored or travels outside the access device. The proposal has been validated by using 560 fingerprints acquired in live by an optical sensor and 560 SRAM-based identifiers.
Dedicated Hardware IP Module for Fingerprint Recognition
(IEEE, 2015-08-06) Martínez Rodríguez, Macarena Cristina; Arjona, Rosario; Brox Jiménez, Piedad; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Gobierno de España; European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER); Universidad de Sevilla
This work presents a dedicated hardware IP module for fingerprints recognition based on a feature, named QFingerMap, which is very suitable for VLSI design. FPGA implementation results of the IP module are given. A demonstrator has been developed to evaluate the IP module behavior in a real scenario.
Hardware Implementation of a Biometric Recognition Algorithm based on In-Air Signature
(IEEE, 2015-06-01) Arjona, Rosario; Romero Moreno, Rocío; Baturone Castillo, María Iluminada; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Ministerio de Economía y Competitividad (MINECO). España; European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER)
This paper presents the design of a prototype for a wearable device that implements a recognition system based on in-air signature into a FPGA that receives data from a 3-axis accelerometer. The Dynamic Time Warping (DTW) algorithm has been analyzed and simplified to reduce the complexity of the hardware architecture that implements the matching in the FPGA. Despite simplification, accuracy of the recognition is maintained and the Equal Error Rate, EER, is 4.21% considering a public database with 120 in-air signatures. A prototype based on a Spartan 6 LX9 microboard connected to an ultralow power ADXL345 accelerometer has been developed. Performance of the prototype working with in-air signatures has been verified with a script developed in Matlab-Simulink. The execution time for matching is 22 ms and the estimated average power consumption of the matching in the FPGA is 26 mW.
Self-Testing Analog Spiking Neuron Circuit
(Institute of Electrical and Electronics Engineers, 2019) El-Sayed, Sarah A.; Camuñas Mesa, Luis Alejandro; Linares Barranco, Bernabé; Stratigopoulos, Haralampos G.; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Hardware-implemented neural networks are foreseen to play an increasing role in numerous applications. In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. In particular, we propose a self-testable version of a spiking neuron circuit. The self-test wrapper is a compact circuit composed of a low-precision ramp generator and a small digital block. The self-test principle is demonstrated on a spiking neuron circuit design in 0.35μm CMOS technology.
Effects of electrical fields on neuroblastoma (N2A) cell differentiation: preliminary results
(Scitepress, 2021) Martín Fernández, Daniel; Pérez García, Pablo; Martín Rubio, María Esther; Daza Navarro, María Paula; Serrano Viseas, Juan Alfonso; Huertas Sánchez, Gloria; Yúfera García, Alberto; Universidad de Sevilla. Departamento de Biología Celular; Universidad de Sevilla. Departamento de Tecnología Electrónica; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo; Junta de Andalucía; Ministerio de Ciencia, Innovación y Universidades (MICINN). España
This work describes Electrical Stimulations (ES) assays on stem cells. The neuroblastoma (N2A) cell linage was submitted to several electrical fields to enable and enhance its differentiation toward neurons. Both Direct Current (DC) and Alternated Current (AC) time dependent electric field protocols were applied to N2A cell culture under differentiation conditions, obtaining different responses. Control and electrically excited samples’ number of differentiated cells and neurite lengths were measure after differentiation. Results showed that DC fields have a strong influence on N2A differentiation since the percentage of differentiated cells and the neurites lengths were the highest. In addition, a significant alignment of neurites measured with the applied electrical field has been detected, which demonstrates the high sensitivity of differentiation processes to electrical field polarity.
Design considerations for a low-noise CMOS image sensor
(SPIE- The International Society for Optical Engineering, 2015) González Márquez, Ana; Charlet, Alexandre; Villegas, Alberto; Jiménez Garrido, Francisco José; Medeiro Hidalgo, Fernando; Domínguez Castro, Rafael; Rodríguez Vázquez, Ángel Benito; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
This paper reports a Low-Noise CMOS Image Sensor. Low-noise operation is achieved owing to the combination of a noise-enhanced pixel, the use of a two-step ADC architecture and the analysis, and the optimization thereof, of the noise contributed by the readout channel. The paper basically gathers the sensor architecture, the ADC converter architecture, the outcome of the noise analysis and some basic characterization data. The general low-noise design framework is discussed in the companion presentation.
Experimental demonstration of real-time image-processing using a VLSI analog programmable array processor
(SPIE- The International Society for Optical Engineering, 2000) Liñán Cembrano, Gustavo; Domínguez Castro, Rafael; Espejo Meana, Servando Carlos; Roca Moreno, Elisenda; Foldesy, Péter; Rodríguez Vázquez, Ángel Benito; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitallyprogrammable analog parallel processing, and distributed image memory —cache— on a common silicon substrate. This chip, designed in a O.5ptm CMOS standard technology contains around 1, 000, 000 transistors, 80% of which operate in analog mode; it is hence one the most complex mixed-signal chip reported to now. Chip functional features are in accordance to the CNN Universal Machine paradigm: cellular, spatial-invariant array architecture; programmable local interactions among cells; randomly-selectable memory of instructions (elementary instructions are defined by specific values of the cell local interactions); random storage/retrieval of intermediate images; capability to complete algorithmic image processing tasks controlled by the user-selected stored instructions and interacting with the cache memory, etc. Thus, as illustrated in this paper, the chip is capable to complete complex spatio-temporal image processing tasks within short computation time ( 200ns for linear convolutions) and using a low power budget (<1.2W for the complete chip). The internal circuitry of the chip has been designed to operate in robust manner with >7-bit equivalent accuracy in the internal analog operations, which has been confirmed by experimental measurements. Hence, to all practical purposes, processing tasks completed by the chip have the same accuracy than those completed by digital processors preceded by 7-bit digital-to-analog converters for image digitalization. Such 7-bit accuracy is enough for most image processing applications. The paper briefly describes the chip architecture and focus mostly on presenting experimental evidences of the chip functionality. Multiscale low-pass and high-pass filtering ofgray-scale images, analog edges extraction, image segmentation, thresholded gradient detection, mathematical morphology operations, shortest path detection in a labyrinth, skeletonizing, image reconstruction, several non-linear type image processing taks like absolute value calculation or gray-scale gradient detection and real-time motion detection in QCIF video sequences are some of the very interesting applications that have been demonstrated as available when using the prototype.
Experimental verification of chaotic encryption of audio using monolithic chaotic modulators
(SPIE- The International Society for Optical Engineering, 1995) Delgado Restituto, Manuel; Rodríguez Vázquez, Ángel Benito; Liñán Reyes, Matías; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
This paper reports the first experimental verification of chaotic encryption of audio signals using integrated circuits. It is based on a g m-C modulator/demodulator analog CMOS IC that implements a 3rd-order nonlinear differential equation. This has been fabricated in 2.4 micrometer double-poly technology and includes on-chip tuning circuitry based on amplitude detection. It is capable of generating controllable continuous-time chaotic signals. Also, measurements demonstrate how to exploit the synchronization between two of them for encrypted transmission. In these experiments, the worst-case signal to noise ratio of the recovered signal is greater than +40 dB (at the low corner of the audio spectrum) with less than -0.2 dB loss of the input signal power. At higher frequencies, the signal-to-noise ratio rises up to +60 dB, while retaining similar losses at the receiver.
Programmable resolution imager for imaging applications
(SPIE- The International Society for Optical Engineering, 2000) Roca Moreno, Elisenda; Soriano Pastor, Germán; Espejo Meana, Servando Carlos; Domínguez Castro, Rafael; Liñán Cembrano, Gustavo; Rodríguez Vázquez, Ángel Benito; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
In this paper a programmable imager with averaging capabilities will be described which is intended for averaging of different groups or sets of pixels formed by n×n kernels, n×m kernels or any group of randomly-selected pixels across the array. This imager is a 64×64 array which uses passive pixels with electronic shutter and anti-blooming structure that can be randomly accessed. The read-out stage includes a sole charge amplifier with programmable gain, a sample-and-hold structure and an analog buffer. This read-out structure is different from other existing imagers with variable resolution since it uses a sole charge amplifier, whereas the conventional structure employs an opamp per column plus another global opamp. This architecture allows a reduction of the fixed-pattern noise observed in standard imagers. The prototype also includes an analog to digital converter which provides the digital output of the images.
Towards a computational approach for collision avoidance with real-world scenes
(SPIE- The International Society for Optical Engineering, 2003) Keil, Matthias Sven; Rodríguez Vázquez, Ángel Benito; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
In the central nervous systems of animals like pigeons and locusts, neurons were identified which signal objects approaching the animal on a direct collision course. In order to timely initiate escape behavior, these neurons must recognize a possible approach (or at least differentiate it from similar but non-threatening situations), and estimate the time-to-collision (ttc). Unraveling the neural circuitry for collision avoidance, and identifying the underlying computational principles, should thus be promising for building vision-based neuromorphic architectures, which in the near future could find applications in cars or planes. Unfortunately, a corresponding computational architecture which is able to handle real-situations (e.g. moving backgrounds, different lighting conditions) is still not available (successful collision avoidance of a robot was demonstrated only for a closed environment). Here we present two computational models for signalling impending collision. These models are parsimonious since they posses only the minimum number of computational units which are essential to reproduce corresponding biological data. Our models show robust performance in adverse situations, such as with approaching low-contrast objects, or with highly textured backgrounds. Furthermore, a condition is proposed under which the responses of our models match the so-called η-function. We finally discuss which components need to be added to our model to convert it into a full-fledged real-world-environment collision detector.
A one-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors
(Institute of Electrical and Electronics Engineers, 1997) Domínguez Castro, Rafael; Espejo Meana, Servando Carlos; Rodríguez Vázquez, Ángel Benito; Carmona Galán, Ricardo; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip.
An error-controlled methodology for approximate hierarchical symbolic analysis
(Institute of Electrical and Electronics Engineers, 2000) Guerra Vinuesa, Oscar; Rodríguez García, Juan D.; Roca Moreno, Elisenda; Fernández Fernández, Francisco Vidal; Rodríguez Vázquez, Ángel Benito; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Limitations of existing approaches for symbolic analysis of large analog circuits are discussed. To address their solution, a new methodology for hierarchical symbolic analysis is introduced. The combination of a hierarchical modeling technique and approximation strategies, comprising circuit reduction, graph-based symbolic solution of circuit equations and matrix-based error control, provides optimum results in terms of speech and quality of results.
A multiplexed mixed-signal fuzzy architecture
(Institute of Electrical and Electronics Engineers, 1998) Vidal Verdú, Fernando; Navas González, Rafael; Rodríguez Vázquez, Ángel Benito; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Analog circuits provide better area/power efficiency than their digital counterparts for low-medium precision requirements. This limit in precision as well as the lack of design tools when compared to the digital approach, imposes a limit of complexity, hence fuzzy analog controllers are usually oriented to fast low-power systems with low-medium complexity. The paper presents a strategy to preserve most of the advantages of an analog implementation, while allowing a notorious increment of the system complexity. Such strategy consists in implementing a reduced number of rules, those that really determine the output in a lattice controller, which we call analog core, then this core is dynamically programmed to perform the computation related to a specific rule set. The data to program the analog core are stored in a memory, and constitutes the whole knowledge base in a kind of virtual rule set. HSPICE simulations from an exemplary controller are shown to illustrate the viability of the proposal.
A 0.18μm CMOS low-noise elliptic low-pass continuous-time filter
(Institute of Electrical and Electronics Engineers, 2005) Fernández Bootello, Juan Francisco; Delgado Restituto, Manuel; Rodríguez Vázquez, Ángel Benito; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
This paper presents a seventh order low-pass continuous-time elliptic filter for use in a high-performance wireline communication receiver. As an additional attribute, the filter provides programmable boost in the pass-band to counteract high frequency components attenuation. The filter shows a nominal cutoff frequency of fc=34 MHz , less than 1dB ripple in the pass-band, and a maximum stop-band rejection of 65dB. The filter also exhibits low noise feature (peak root spectral noise density below 56nV√Hz) and high linearity (more than 64dB of MTPR for a DMT signal of 0.5Vpp amplitude). It has been designed in a 0.18μm CMOS technology and it is compliant with industrial operation conditions (-40 to 85° C temperature variation and ± 5% power supply deviation). Simulations show a typical power consumption of 450 mW @ 1.8V supply.
Tactile retina for slip detection
(Institute of Electrical and Electronics Engineers, 2006) Maldonado López, Rocío; Vidal Verdú, Fernando; Liñán Cembrano, Gustavo; Roca Moreno, Elisenda; Rodríguez Vázquez, Ángel Benito; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
The interest in tactile sensors is increasing as their use in complex unstructured environments is demanded, like in telepresence, minimal invasive surgery, robotics etc. The array of pressure data provided by these devices can be treated with different image processing algorithms to extract the required information. However, as in the case of vision chips or artificial retinas, problems arise when the array size and the computation complexity increase. Having a look at the skin, the information collected by every mechanoreceptor is not sent to the brain for its processing, but some complex pre-processing is performed to fit the limited throughput of the nervous system. This is specially important for high bandwidth demanding tasks. Experimental works report that neural response of skin mechanoreceptors encodes the change in local shape from an offset level rather than the absolute force or pressure distributions. Something similar happens in the retina, which implements a spatio-temporal averaging. We propose the same strategy in tactile preprocessing, and we show preliminary results illustrated for the case of slip detection, which is certainly demanding in computing requirements.
Robust symmetric multiplication for programmable analog VLSI array processing
(Institute of Electrical and Electronics Engineers, 2006) Domínguez Matas, Carlos; Carmona Galán, Ricardo; Sánchez Fernández, Francisco J.; Rodríguez Vázquez, Ángel Benito; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
This paper presents an electrically programmable analog multiplier. The circuit performs the multiplication between an input variable and an electrically selectable scaling factor. The multiplier is divided in several blocks: a linearized transconductor, binary weighted current mirrors and a differential to single-ended current adder. This paper shows the advantages introduced using a linearized OTA-based multiplier. The circuit presented renders higher linearity and symmetry in the output current than a previously reported single-transistor multiplier. Its inclusion in an array processor based on CNN allows for a more accurate implementation of the processing model and a more robust weight distribution scheme than those found in previous designs.
Generation and design of sinusoidal oscillators using OTAS
(Institute of Electrical and Electronics Engineers, 1988) Linares Barranco, Bernabé; Rodríguez Vázquez, Ángel Benito; Huertas Díaz, José Luis; Sánchez Sinencio, Edgar; Hoyle, Javier J.; Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
The design of voltage-controlled oscillators (VCOs) using operational transconductance amplifiers (OTAs) is discussed. Several oscillator structures are proposed. They use only OTAs and capacitors (OTA-C) and are very appropriate for silicon monolithic implementations. The resulting oscillation frequencies are proportional to the transconductance of the OTA and this makes the reported structures well suited for building VCOs. Amplitude stabilization circuits using both automatic gain control (AGC) mechanisms and limitation schemes that are compatible with OTA-C oscillators are studied. Experimental results from breadboard prototypes are included, showing the good potential of OTA-based oscillators for high-frequency VCO operation.

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