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Now showing items 21-30 of 32
Presentation
Offset-compensated comparator with full-input range in 150nm FDSOI CMOS-3d technology
(Institute of Electrical and Electronics Engineers, 2010)
This paper addresses an offset-compensated comparator with full-input range in the 150nm FDSOI CMOS- 3D technology from MIT- Lincoln Laboratory. The comparator discussed here makes part of a vision system. Its architecture ...
Presentation
A processing element architecture for high-density focal plane analog programmable array processors
(Institute of Electrical and Electronics Engineers, 2002)
The architecture of the elementary Processing Element - PE- used in a recently designed 128×128 Focal Plane Analog Programmable Array Processor is presented. The PE architecture contains the required building blocks to ...
Presentation
A multimode gray-scale CMOS optical sensor for visual computers
(Institute of Electrical and Electronics Engineers, 2002)
This paper presents a new multimode optical sensor architecture for the optical interface of Visual CNN (cellular neural net) chips. The sensor offers to the user the possibility of choosing the photo-sensitive device as ...
Presentation
A mismatch-insensitive high-accuracy high-speed continuous-time current comparator in low voltage CMOS
(Institute of Electrical and Electronics Engineers, 1997)
This paper presents a CMOS current comparator which employs nonlinear feedback to obtain high-accuracy (down to 1.5 pA) and high-speed for low input currents (8 ns@50 nA). This structure is much faster for low currents ...
Presentation
In-pixel ADC for a vision architecture on CMOS-3D technology
(Institute of Electrical and Electronics Engineers, 2010)
This paper addresses the design of an 8-bit single-slope in-pixel ADC for a 3D chip architecture intended for airborne surveillance and reconnaissance applications. The 3D chip architecture comprises a sensor layer with a ...
Presentation
ACE16k: A programmable focal plane vision processor with 128 x 128 resolution
(European Conference on Circuit Theory and Design, 2001)
This paper presents a new generation 128x128 Focal Plane Analog Programmable Array Processor (FPAPAP), from a system level perspective. The design has recently sent to fabrication in a 0.35μm standard digital 1P-5M ...
Presentation
Tactile on-chip pre-processing with techniques from artificial retinas
(The International Society for Optical Engineering - SPIE, 2005)
The interest in tactile sensors is increasing as their use in complex unstructured environments is demanded, like in tele-presence, minimal invasive surgery, robotics etc. The matrix of pressure data these devices provide ...
Presentation
Programmable resolution imager for imaging applications
(SPIE- The International Society for Optical Engineering, 2000)
In this paper a programmable imager with averaging capabilities will be described which is intended for averaging of different groups or sets of pixels formed by n×n kernels, n×m kernels or any group of randomly-selected ...
Presentation
Some design trade-offs for large CNN chips using small-size transistors
(Institute of Electrical and Electronics Engineers, 1997)
Small-size MOS transistors (MOST) exhibit a bunch of second-order effects which limit their application to design Cellular Neural Network (CNN) chips. The inverse dependency of mismatch with transistor sizes may result in ...
Presentation
ACE16K: A 128×128 focal plane analog processor with digital I/O
(Institute of Electrical and Electronics Engineers, 2002)
This paper presents a new generation 128×128 focal-plane analog programmable array processor (FPAPAP), from a system level perspective, which has been manufactured in a 0.35 μm standard digital 1P-5M CMOS technology. The ...