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Mostrando ítems 1-8 de 8
Ponencia
Wi-FLIP: A wireless smart camera based on a focal-plane low-power image processor
(Institute of Electrical and Electronics Engineers, 2011)
This paper presents Wi-FLIP, a vision-enabled WSN node resulting from the integration of FLIP-Q, a prototype vision chip, and Imotel, a commercial WSN platform. In Wi-FLIP, image processing is not only constrained to the ...
Ponencia
High-dynamic range tone-mapping algorithm for focal plane processors
(The International Society for Optics and Photonics, 2011)
This paper presents a Dynamic Range improvement technique which is specially well-suited to be implemented in Focal Plane Processors (FPP) due to its very limited computing requirements since only local memories, little ...
Ponencia
Live demonstration: Real-time high dynamic range video acquisition using in-pixel adaptive content-aware tone mapping compression
(Institute of Electrical and Electronics Engineers, 2015)
This demonstration targets the acquisition of realtime video sequences involving High Dynamic Range (HDR) scenes. Adaptation to different illumination conditions while preserving contrast is achieved by using a sensor chip, ...
Ponencia
Control and acquisition system for a high dynamic range CMOS image sensor
(Institute of Electrical and Electronics Engineers, 2012)
A control and acquisition system for the visualization of the images captured with a High Dynamic Range (HDR) CMOS Image Sensor is developed. The image sensor is inserted in a PCB system, which performs low level control, ...
Ponencia
Demo: Real-time remote reporting of active regions with Wi-FLIP
(Institute of Electrical and Electronics Engineers, 2011)
This paper describes a real-time application programmed into Wi-FLIP, a wireless smart camera resulting from the integration of FLIP-Q, a focal-plane low-power image processor, and Imote2, a commercial WSN platform. The ...
Ponencia
Offset-compensated comparator with full-input range in 150nm FDSOI CMOS-3d technology
(Institute of Electrical and Electronics Engineers, 2010)
This paper addresses an offset-compensated comparator with full-input range in the 150nm FDSOI CMOS- 3D technology from MIT- Lincoln Laboratory. The comparator discussed here makes part of a vision system. Its architecture ...
Ponencia
In-pixel ADC for a vision architecture on CMOS-3D technology
(Institute of Electrical and Electronics Engineers, 2010)
This paper addresses the design of an 8-bit single-slope in-pixel ADC for a 3D chip architecture intended for airborne surveillance and reconnaissance applications. The 3D chip architecture comprises a sensor layer with a ...
Ponencia
A QCIF 145dB imager for focal plane processor chips using a tone mapping technique in standard 0.35μm CMOS technology
(2011)
This paper presents a QCIF HDR imager where visual information is simultaneously captured and adaptively compressed by means of an in-pixel tone mapping scheme [1]. The tone mapping curve (TMC) is calculated from a ...