Listar Artículos (Instituto de Microelectrónica de Sevilla (IMSE-CNM)) por autor "Domínguez Castro, Rafael"
Mostrando ítems 1-15 de 15
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A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
(Institute of Electrical and Electronics Engineers, 1997)This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) ...
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A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
(Institute of Electrical and Electronics Engineers, 2004)This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of ...
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A Bio-Inspired Two-Layer Mixed-Signal Flexible Programmable Chip for Early Vision
(Institute of Electrical and Electronics Engineers, 2003)A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has ...
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A CMOS 0.8 μm fully differential current mode buffer for HF SI circuits
(Elsevier, 1998)We present a high-frequency fully-differential current-mode buffer to interface off-chip currents with no significant ...
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ACE16K: The Third Generation of Mixed-Signal SIMD-CNN ACE Chips Toward VSoCs
(Institute of Electrical and Electronics Engineers, 2004)Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible ...
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An 0.5-μm CMOS analog random access memory chip for TeraOPS speed multimedia video processing
(Institute of Electrical and Electronics Engineers, 1999)Data compressing, data coding, and communications in object-oriented multimedia applications like telepresence, computer-aided ...
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Analog Neural Programmable Optimizers in CMOS VLSI Technologies
(Institute of Electrical and Electronics Engineers, 1992)A 3-μm CMOS IC is presented demonstrating the concept of an analog neural system for constrained optimization. A serial ...
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CMOS optical-sensor array with high output current levels and automatic signal-range centring
(Institution of Engineering and Technology, 1994)A CMOS compatible photosensor with high output current levels, and an area-efficient scheme for automatic signal-range ...
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Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks
(Institute of Electrical and Electronics Engineers, 1993)This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) ...
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Global design of analog cells using statistical optimization techniques
(Springer, 1994)We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. ...
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Robust high-accuracy high-speed continuous-time CMOS current comparator
(Institution of Engineering and Technology, 1997)The authors present a CMOS current comparator which employs nonlinear negative feedback to obtain high-accuracy (down to ...
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Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS
(Institute of Electrical and Electronics Engineers, 2004)Based on studies of the mammalian retina, a bioinspired model for mixed-signal array processing has been implemented on ...
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SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips
(Wiley-Blackwell, 1999)This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing ...
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Smart-Pixel Cellular Neural Networks in Analog Current-Mode CMOS Technology
(Institute of Electrical and Electronics Engineers, 1994)This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. ...
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Switched-capacitor neural networks for linear programming
(Institution of Engineering and Technology, 1988)A circuit for online solving of linear programming problems is presented. The circuit uses switched-capacitor techniques ...