Listar Artículos (Instituto de Microelectrónica de Sevilla (IMSE-CNM)) por autor "Delgado Restituto, Manuel"
Mostrando ítems 1-18 de 18
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A Chaotic Switched-Capacitor Circuit for 1/f Noise Generation
(Institute of Electrical and Electronics Engineers, 1992)A switched-capacitor circuit is reported for the generation of 1 / fYnoise. The circuit is described by a chaotic first-order ...
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A Low-Power Programmable Neural Spike Detection Channel With Embedded Calibration and Data Compression
(Institute of Electrical and Electronics Engineers, 2012)This paper reports a programmable 400 μm pitch neural spike recording channel, fabricated in a 130 nm standard CMOS ...
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A mixed-signal integrated circuit for FM-DCSK modulation
(Institute of Electrical and Electronics Engineers, 2005)This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential ...
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A switched-capacitor broadband noise generator for CMOS VLSI
(Institution of Engineering and Technology, 1991)A switched-capacitor circuit is reported for the generation of broadband white noise in MOS VLSI. It is based on the ...
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Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits
(Institute of Electrical and Electronics Engineers, 2009)We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with ...
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An ultralow-power mixed-signal back end for passive sensor UHF RFID transponders
(Institute of Electrical and Electronics Engineers, 2012)This paper describes the design of mixed-signal back end for an ultrahigh-frequency sensor-enabled radio-frequency ...
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CMOS 2.4μm chaotic oscillator: Experimental verification of chaotic encryption of audio
(Institution of Engineering and Technology, 1996)The Letter reports the first experimental verification of chaotic encryption of audio using custom monolithic chaotic ...
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Design considerations for integrated continuous-time chaotic oscillators
(Institute of Electrical and Electronics Engineers, 1998)This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation ...
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Enhanced Sensitivity of CMOS Image Sensors by Stacked Diodes
(Institute of Electrical and Electronics Engineers, 2016)We have investigated and compared the performance of photodiodes built with stacked p/n junctions operating in parallel ...
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Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+
(Institute of Electrical and Electronics Engineers, 2004)We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications ...
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Integrated chaos generators
(Institute of Electrical and Electronics Engineers, 2002)This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.
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Matrix Methods for the Dynamic Range Optimization of Continuous-TimeGm-CFilters
(Institute of Electrical and Electronics Engineers, 2008)This paper presents a synthesis procedure for the optimization of the dynamic range of continuous-time fully differential ...
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Nonlinear switched-current CMOS IC for random signal generation
(Institution of Engineering and Technology, 1993)A nonlinear switched-current circuit is presented that implements a chaotic algorithm for the generation of broadband, ...
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Offset-calibration with Time-Domain Comparators Using Inversion-mode Varactors
(Institute of Electrical and Electronics Engineers, 2019)This paper presents a differential time-domain comparator formed by two voltage controlled delay lines, one per input ...
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Phase Synchronization Operator for On-Chip Brain Functional Connectivity Computation
(Institute of Electrical and Electronics Engineers, 2019)This paper presents an integer-based digital processor for the calculation of phase synchronization between two neural ...
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Switched-Current Chaotic Neurons
(Institution of Engineering and Technology, 1994)The Letter presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural ...
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System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor
(Institute of Electrical and Electronics Engineers, 2017)This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and ...
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Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm
(Institute of Electrical and Electronics Engineers, 2011)A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map ...