Listar Artículos (Instituto de Microelectrónica de Sevilla (IMSE-CNM)) por título
Mostrando ítems 245-264 de 278
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Artículo
Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS
(Institute of Electrical and Electronics Engineers, 2004)Based on studies of the mammalian retina, a bioinspired model for mixed-signal array processing has been implemented on ...
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Secure combination of iot and blockchain by physically binding iot devices to smart non-fungible tokens using pufs
(Multidisciplinary Digital Publishing Institute (MDPI), 2021)Non-fungible tokens (NFTs) are widely used in blockchain to represent unique and non-interchangeable assets. Current NFTs ...
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Ponencia
Securing Minutia Cylinder Codes for Fingerprints through Physically Unclonable Functions: An Exploratory Study
(IEEE, 2018-07-16)A number of personal devices, such as smartphones, have incorporated fingerprint recognition solutions for user authentication ...
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Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validation
(Elsevier, 2016)This paper presents a simple but accurate semi-empirical model especially focused on 65 nm MOST (MOS transistor) technologies ...
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Side-channel analysis of the modular inversion step in the RSA key generation algorithm
(John Wiley & Sons, 2016)This paper studies the security of the RSA key generation algorithm with regard to side-channel analysis and presents a ...
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Simple evaluation of the nonlinearity signature of an ADC using a spectral approach
(2008)This work presents a new method to estimate the nonlinearity characteristics of analog-to-digital converters (ADCs). The ...
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Single-Exposure HDR Technique Based on Tunable Balance Between Local and Global Adaptation
(Institute of Electrical and Electronics Engineers, 2016)This brief describes a high-dynamic-range technique that compresses wide ranges of illuminations into the available signal ...
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SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips
(Wiley-Blackwell, 1999)This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing ...
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Smart imaging for power-efficient extraction of Viola-Jones local descriptors
(Society of Photo-Optical Instrumentation Engineers, 2014)In computer vision, local descriptors permit to summarize relevant visual cues through feature vectors. These vectors ...
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Smart-Pixel Cellular Neural Networks in Analog Current-Mode CMOS Technology
(Institute of Electrical and Electronics Engineers, 1994)This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. ...
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SMASH ΔΣ modulator with adderless feed-forward loop filter
(Wiley-Blackwell, 2017)A novel cascade ΔΣ modulator, which combines the benefits of sturdy MASH (SMASH) topology and feed-forward loop filter, ...
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Sorting networks implemented as νMOS circuits
(Institute of Electrical and Electronics Engineers, 1998)A new realisation for n-input sorters is presented. Resorting to the neuron-MOS (νMOS) concept and to an adequate electrical scheme, a compact and efficient implementation is obtained.
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State merging and state splitting via state assignment: a new FSM synthesis algorithm
(Institute of Electrical and Electronics Engineers, 1994)The authors describe a state assignment algorithm for FSMs which produces an assignment of non-necessarily distinct, and ...
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Sun Sensor Based on a Luminance Spiking Pixel Array
(Institute of Electrical and Electronics Engineers, 2017)We present a novel sun sensor concept. It is the very first sun sensor built with an address event representation spiking ...
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Switched-capacitor neural networks for linear programming
(Institution of Engineering and Technology, 1988)A circuit for online solving of linear programming problems is presented. The circuit uses switched-capacitor techniques ...
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Switched-Current Chaotic Neurons
(Institution of Engineering and Technology, 1994)The Letter presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural ...
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Symbolic analysis of analog circuits containing voltage mirrors
(Springer, 2010)The pathological elements voltage mirror (VM) and current mirror (CM) have shown advantages in analog behavioral modeling ...
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System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor
(Institute of Electrical and Electronics Engineers, 2017)This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and ...
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Testing mixed-signal cores: a practical oscillation-based test in an analog macrocell
(Institute of Electrical and Electronics Engineers, 2002)A formal set of design decisions can aid in using oscillation-based test (OBT) for analog subsystems in SoCs. The goal is ...
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TFET-based Well Capacity Adjustment in Active Pixel Sensor for Enhanced High Dynamic Range
(Institute of Electrical and Electronics Engineers, 2017)We present a Tunnel Field-Effect Transistor (TFET)-based pixel circuit for well capacity adjustment that does not require ...