Listar Artículos (Instituto de Microelectrónica de Sevilla (IMSE-CNM)) por título
Mostrando ítems 257-276 de 278
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State merging and state splitting via state assignment: a new FSM synthesis algorithm
(Institute of Electrical and Electronics Engineers, 1994)The authors describe a state assignment algorithm for FSMs which produces an assignment of non-necessarily distinct, and ...
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Sun Sensor Based on a Luminance Spiking Pixel Array
(Institute of Electrical and Electronics Engineers, 2017)We present a novel sun sensor concept. It is the very first sun sensor built with an address event representation spiking ...
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Switched-capacitor neural networks for linear programming
(Institution of Engineering and Technology, 1988)A circuit for online solving of linear programming problems is presented. The circuit uses switched-capacitor techniques ...
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Switched-Current Chaotic Neurons
(Institution of Engineering and Technology, 1994)The Letter presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural ...
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Symbolic analysis of analog circuits containing voltage mirrors
(Springer, 2010)The pathological elements voltage mirror (VM) and current mirror (CM) have shown advantages in analog behavioral modeling ...
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System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor
(Institute of Electrical and Electronics Engineers, 2017)This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and ...
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Testing mixed-signal cores: a practical oscillation-based test in an analog macrocell
(Institute of Electrical and Electronics Engineers, 2002)A formal set of design decisions can aid in using oscillation-based test (OBT) for analog subsystems in SoCs. The goal is ...
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TFET-based Well Capacity Adjustment in Active Pixel Sensor for Enhanced High Dynamic Range
(Institute of Electrical and Electronics Engineers, 2017)We present a Tunnel Field-Effect Transistor (TFET)-based pixel circuit for well capacity adjustment that does not require ...
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The active-input regulated-cascode current mirror
(Institute of Electrical and Electronics Engineers, 1994)A continuous-time current mirror circuit is presented that combines an active input and a regulated cascode output. The ...
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The bio-oscillator: A circuit for cell-culture assays
(Institute of Electrical and Electronics Engineers, 2015)A system for cell-culture real-time monitoring using an oscillation-based approach is proposed. The system transforms a ...
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The Influence of MPPT Algorithms in the Lifespan of the Capacitor Across the PV Array
(Institute of Electrical and Electronics Engineers, 2022)PV systems efficiency highly depends on the MPPT strategy to be implemented in the PV converter. Many MPPT methods on the ...
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The stochastic I-Pot: A circuit block for programming bias currents
(Institute of Electrical and Electronics Engineers, 2007)In this brief, we present the “Stochastic I-Pot.” It is a circuit element that allows for digitally programming a precise ...
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Toward visual microprocessors
(Institute of Electrical and Electronics Engineers, 2002)This paper outlines motivations and models underlying the design of visual microprocessors based on the cellular neural ...
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Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm
(Institute of Electrical and Electronics Engineers, 2011)A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map ...
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Trusted Cameras on Mobile Devices Based on SRAM Physically Unclonable Functions
(MDPI, 2018)Nowadays, there is an increasing number of cameras placed on mobile devices connected to the Internet. Since these cameras ...
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Tunable Low Noise Amplifier Implementation With Low Distortion Pseudo-Resistance for in Vivo Brain Activity Measurement
(Institute of Electrical and Electronics Engineers, 2014)This paper presents a low power neural signal amplifier with tunable cut-off frequencies. The presented compact amplifier, ...
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Two-phase RTD-CMOS pipelined circuits
(Institute of Electrical and Electronics Engineers, 2012)MOnostable-BIstable Logic Element (MOBILE) networks can be operated in a gate-level pipelined fashion (nanopipeline) ...
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Ultralow-power processing array for image enhancement and edge detection
(Institute of Electrical and Electronics Engineers, 2012)This paper presents a massively parallel processing array designed for the 0.13-μm 1.5-V standard CMOS base process of a ...
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Using Building Blocks to Design Analog Neuro-Fuzzy Controllers
(Institute of Electrical and Electronics Engineers, 1995)We present a parallel architecture for fuzzy controllers and a methodology for their realization as analog CMOS chips for ...
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Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology
(Wiley-Blackwell, 1997)This paper uses a CAD methodology proposed by the authors to design a low-power 2nd-order Sigma-Delta Modulator (ΣΔM). ...