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Artículo
Design methodology for low-jitter differential clock recovery circuits in high performance ADCs
(Springer, 2016)
This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100fsrms) for high-performance ADCs. The key ideas of the design ...
Artículo
RTD-CMOS pipelined networks for reduced power consumption
(Institute of Electrical and Electronics Engineers, 2011)
The incorporation of resonant tunneling diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance, producing higher circuit speed, reduced component count, and/or lower power consumption. ...
Artículo
Efficient realisation of MOS-NDR threshold logic gates
(Wiley Open Access, 2009-11-05)
A novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms of area and power consumption, has been performed to demonstrate that the proposed circuit is ...