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Mostrando ítems 11-20 de 80
Ponencia
Hysteresis based neural oscillators for VLSI implementations
(Institute of Electrical and Electronics Engineers, 1991)
The actual tendency in most of the work that is being done in VLSI neural network research is to use the simplest possible models to perform the desired tasks. This yields to the use of sigmoidal type neurons that have ...
Artículo
A spatial contrast retina with on-chip calibration for neuromorphic spike-based AER vision systems
(Institute of Electrical and Electronics Engineers, 2007)
We present a 32 32 pixels contrast retina microchip that provides its output as an address event representation (AER) stream. Spatial contrast is computed as the ratio between pixel photocurrent and a local average between ...
Artículo
Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links
(Institute of Electrical and Electronics Engineers, 2016)
Asynchronous handshaken interchip links are very popular among neuromorphic full-custom chips due to their delay-insensitive and high-speed properties. Of special interest are those links that minimize bit-line transitions ...
Artículo
A neuromorphic cortical-layer microchip for spike-based event processing vision systems
(Institute of Electrical and Electronics Engineers, 2006)
We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing systems. The microchip computes 2-D convolutions of video information represented in AER format ...
Artículo
On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing
(IEEE Computer Society, 2008)
In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The chip is a first experimental prototype of reduced size to validate the implemented circuits ...
Ponencia
CMOS analog neural network systems based on oscillatory neurons
(Institute of Electrical and Electronics Engineers, 1992)
This paper addresses the design of two neural network systems based on the use of pulsing neurons. Each neuron is built as a simple voltage controlled oscillator (VCO) whose control voltage makes the circuit to oscillate ...
Artículo
CAVIAR: A 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and tracking
(Institute of Electrical and Electronics Engineers, 2009)
This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating system inspired by the physiology of the nervous system. CAVIAR uses the asychronous address-event ...
Artículo
A real-time clustering microchip neural engine
(Institute of Electrical and Electronics Engineers, 1996)
This paper presents an analog current-mode VLSI implementation of an unsupervised clustering algorithm. The clustering algorithm is based on the popular ART1 algorithm, but has been modified resulting in a more VLSI-friendly ...
Artículo
Log-domain implementation of complex dynamics reaction-diffusion neural networks
(Institute of Electrical and Electronics Engineers, 2003)
In this paper, we have identified a second-order reaction-diffusion differential equation able to reproduce through parameter setting different complex spatio-temporal behaviors. We have designed a log-domain hardware that ...
Ponencia
Nonlinear time-domain macromodeling of OTA circuits
(Institute of Electrical and Electronics Engineers, 1989)
The authors present an accurate nonlinear macromodel of the operational transconductance amplifier (OTA) which is suitable for the transient simulation of OTA-based CMOS analog integrated circuits. As compared to device-level ...