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Mostrando ítems 21-27 de 27
Artículo
ACE16K: The Third Generation of Mixed-Signal SIMD-CNN ACE Chips Toward VSoCs
(Institute of Electrical and Electronics Engineers, 2004)
Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-μm technologies knocking at the door of designers, we can ...
Ponencia
ACE16k: A programmable focal plane vision processor with 128 x 128 resolution
(European Conference on Circuit Theory and Design, 2001)
This paper presents a new generation 128x128 Focal Plane Analog Programmable Array Processor (FPAPAP), from a system level perspective. The design has recently sent to fabrication in a 0.35μm standard digital 1P-5M ...
Ponencia
Tactile on-chip pre-processing with techniques from artificial retinas
(The International Society for Optical Engineering - SPIE, 2005)
The interest in tactile sensors is increasing as their use in complex unstructured environments is demanded, like in tele-presence, minimal invasive surgery, robotics etc. The matrix of pressure data these devices provide ...
Artículo
Macromodelling for analog design and robustness boosting in bio-inspired computing models
(Society of Photo-Optical Instrumentation Engineers, 2005)
Setting specifications for the electronic implementation of biological neural-network-like vision systems on-chip is not straightforward, neither it is to simulate the resulting circuit. The structure of these systems leads ...
Ponencia
Programmable resolution imager for imaging applications
(SPIE- The International Society for Optical Engineering, 2000)
In this paper a programmable imager with averaging capabilities will be described which is intended for averaging of different groups or sets of pixels formed by n×n kernels, n×m kernels or any group of randomly-selected ...
Ponencia
ACE16K: A 128×128 focal plane analog processor with digital I/O
(Institute of Electrical and Electronics Engineers, 2002)
This paper presents a new generation 128×128 focal-plane analog programmable array processor (FPAPAP), from a system level perspective, which has been manufactured in a 0.35 μm standard digital 1P-5M CMOS technology. The ...
Ponencia
The CNNUC3: an analog I/O 64x64 CNN universal machine chip prototype with 7-bit analog accuracy
(Institute of Electrical and Electronics Engineers, 2000)
This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitally-programmable analog parallel processing, and distributed image memory (cache) on a common silicon substrate. ...