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Mostrando ítems 11-20 de 24
Ponencia
Continuous-time cascaded ΣΔ modulators for VDSL: A comparative study
(The International Society for Optical Engineering - SPIE, 2005)
This paper describes new cascaded continuous-time ΣΔ modulators intended to cope with very high-rate digital subscriber line specifications, i.e 12-bit resolution within a 20-MHz signal bandwidth. These modulators have ...
Ponencia
Effect of Clock Jitter Error on the Performance Degradation of Multi-bit Continuous-Time ΣΔ Modulators With NRZ DAC
(2005)
This paper analyses the effect of the clock jitter error in multi-bit continuous-time ΣΔ modulators with non-return-to-zero feedback waveform. Derived expressions show that the jitter-induced noise power can be separated ...
Ponencia
ACE 16k based stand-alone system for real-time pre-processing tasks
(The International Society for Optical Engineering - SPIE, 2005)
This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's architecture has been implemented and tested using an ACE16k chip and a Xilinx xc4028xl FPGA. The ...
Ponencia
On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis
(The International Society for Optical Engineering - SPIE, 2005)
Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. ...
Ponencia
Design and electrical implementation of a 1.8-V multistandard switched-current ΣΔ modulator
(2005)
This paper describes the design and electrical implementation of a 1.8-V, 0.18mm CMOS reconfigurable switched-current SD modulator for multistandard (Bluetooth, WCDMA) communication systems. The modulator topology is an ...
Ponencia
AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems
(Neural Information Processing Systems Foundation, 2005)
A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the address-eventrepresentation (AER) is demonstrated. The system includes a retina chip, two convolution chips, a ...
Ponencia
A Direct Synthesis Method of Cascaded Continuous-Time Sigma-Delta Modulators
(2005)
This paper presents an efficient method to synthesize cascaded sigma-delta modulators implemented with continuous-time circuits. It is based on the direct synthesis of the whole cascaded architecture in the continuous-time ...
Ponencia
Analysis of Clock Jitter Error in Multibit Continuous-Time ΣΔ modulators with NRZ Feedback Waveform
(Institute of Electrical and Electronics Engineers, 2005)
This paper presents a detailed study of the clock jitter error in multibit continuous-time ΣΔ modulators with non-return-to-zero feedback waveform. Closed-form expressions are derived for the in-band error power and the ...
Ponencia
Simulation-based high-level synthesis of Nyquist-rate data converters using MATLAB/SIMULINK
(The International Society for Optical Engineering - SPIE, 2005)
This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB®. The embedded simulator uses SIMULINK® C-coded ...
Ponencia
An Embedded 12-bit 80MS/s A/D/A Interface for Power-Line Communications in 0.13μm Pure Digital CMOS Technology
(Institute of Electrical and Electronics Engineers, 2005)
This paper presents an embedded interface, comprising both A/D and D/A converters, which has been implemented in a 0.13μm pure digital CMOS technology. The interface is integrated in a system for high-performance broad-band ...