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Ponencia
On-chip Reduced-code Static Linearity Test of Vcm-based Switching SAR ADCs Using an Incremental Analog-to-digital Converter
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
This paper describes a BIST technique for the static linearity test of Vcm-based successive-approximation analog-to-digital converters (SAR ADCs). We discuss the application of reduced-code techniques for the Vcm-based SAR ...
Ponencia
Static Linearity BIST for Vcm-based Switching SAR ADCs Using a Reduced-code Measurement Technique
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
This work presents a reduced-code strategy for the static linearity self-testing of Vcm -based successive-approximation analog to digital converters (SAR ADCs). These techniques take advantage of the repetitive operation ...
Ponencia
Vertically Stacked CMOS-compatible Photodiodes for Scanning Electron Microscopy
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
This paper reports the use of vertically stacked photodiodes as compact solid-state spectrometers for transmission scanning electron microscopy. SEM microscopes operate by illuminating the sample with accelerated electrons. ...
Ponencia
VersaTile Convolutional Neural Network Mapping on FPGAs
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Convolutional Neural Networks (ConvNets) are directed acyclic graphs with node transitions determined by a 1 set of configuration parameters. In this paper, we describe a 2 dynamically configurable hardware architecture ...