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Ponencia
Design Flow to Evaluate the Performance of Ring Oscillator PUFs on FPGAs
(Institute of Electrical and Electronics Engineers. IEEE, 2021)
This work presents a unified framework to design, implement and evaluate the performance of Ring Oscillator Physical Unclonable Functions (RO PUFs) on FPGAs. The design flow uses a Digital Signal Processing (DSP) tool ...
Ponencia
Demo: Results of 'iCaveats', a Project on the Integration of Architectures and Components for Embedded Vision
(ACM Digital Library, 2018)
iCaveats is a Project on the integration of components and architectures for embedded vision in transport and security applications. A compact and efficient implementation of autonomous vision systems is difficult to be ...
Ponencia
Automated experimental setup for EM cartography to enhance EM attacks
(2022)
Side-channel attacks are a real threat, exploiting and revealing the secret data stored in our electronic devices just analyzing the leaked information of the cryptographic modules during their normal encryption/decryption ...
Ponencia
Vertically Stacked CMOS-compatible Photodiodes for Scanning Electron Microscopy
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
This paper reports the use of vertically stacked photodiodes as compact solid-state spectrometers for transmission scanning electron microscopy. SEM microscopes operate by illuminating the sample with accelerated electrons. ...
Ponencia
VersaTile Convolutional Neural Network Mapping on FPGAs
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Convolutional Neural Networks (ConvNets) are directed acyclic graphs with node transitions determined by a 1 set of configuration parameters. In this paper, we describe a 2 dynamically configurable hardware architecture ...