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evercodeML: a formal language for SoC integration

dc.creatorVillar de Ossorno, José Ignacioes
dc.creatorJuan Chico, Jorgees
dc.creatorGuerrero Martos, Davides
dc.creatorBellido Díaz, Manuel Jesúses
dc.creatorViejo Cortés, Juliánes
dc.date.accessioned2021-02-12T09:12:11Z
dc.date.available2021-02-12T09:12:11Z
dc.date.issued2015
dc.identifier.citationVillar de Ossorno, J.I., Juan Chico, J., Guerrero Martos, D., Bellido Díaz, M.J. y Viejo Cortés, J. (2015). evercodeML: a formal language for SoC integration. En ESLsyn: 2015 Electronic System Level Synthesis Conference San Francisco, CA: IEEE Computer Society.
dc.identifier.isbn979-1-0922-7912-2es
dc.identifier.issn2117-4628es
dc.identifier.urihttps://hdl.handle.net/11441/104879
dc.description.abstractComplex SoC design devote a great part of the developing time to module integration tasks. The necessity of automating system integration at high-level has yield to the development of module description languages like IP-XACT. However, the available options today still lack advanced parametrization capabilities needed to design complex systems with very heterogeneous IP-cores and module providers. This contribution introduces a formal language for SoC integration that overcomes these limitations.es
dc.description.sponsorshipMinisterio de Ciencia e Innovación TEC2011-27936 (HIPERSYS)es
dc.formatapplication/pdfes
dc.format.extent4es
dc.language.isoenges
dc.publisherIEEE Computer Societyes
dc.relation.ispartofESLsyn: 2015 Electronic System Level Synthesis Conference (2015).
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectFPGAes
dc.subjectSoCes
dc.subjectIP-corees
dc.subjectIP-XACTes
dc.titleevercodeML: a formal language for SoC integrationes
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/submittedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Tecnología Electrónicaes
dc.relation.projectIDTEC2011-27936 (HIPERSYS)es
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/7365121es
dc.contributor.groupUniversidad de Sevilla. TIC204: Investigación y Desarrollo Digitales
dc.eventtitleESLsyn: 2015 Electronic System Level Synthesis Conferencees
dc.eventinstitutionSan Francisco, CAes
dc.relation.publicationplaceNew York, USAes
dc.contributor.funderMinisterio de Ciencia e Innovación (MICIN). Españaes

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