Ponencia
Automatic logic synthesis for parallel alternating latches clocking schemes
Autor/es | Guerrero Martos, David
Bellido Díaz, Manuel Jesús Juan Chico, Jorge Millán Calderón, Alejandro Ruiz de Clavijo Vázquez, Paulino Ostúa Arangüena, Enrique Viejo Cortés, Julián |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Fecha de publicación | 2007 |
Fecha de depósito | 2021-02-11 |
Publicado en |
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ISBN/ISSN | 0277-786X |
Resumen | This paper proposes a VHDL coding technique that allows for the automatic synthesis of digital circuits using the so
called Parallel Alternating Latches Clocking Schemes (PALACS). The proposed method greatly improves ... This paper proposes a VHDL coding technique that allows for the automatic synthesis of digital circuits using the so called Parallel Alternating Latches Clocking Schemes (PALACS). The proposed method greatly improves the applicability of PALACS and its benefits. This technique is verified through design examples in three different CMOS processes and using logic level simulation, with successful results in all the cases. |
Agencias financiadoras | Ministerio de Educación y Ciencia (MEC). España |
Identificador del proyecto | TEC-2004-00840-MIC |
Cita | Guerrero Martos, D., Bellido Díaz, M.J., Juan Chico, J., Millán Calderón, A., Ruiz de Clavijo Vázquez, P., Ostúa Arangüena, E. y Viejo Cortés, J. (2007). Automatic logic synthesis for parallel alternating latches clocking schemes. En Microtechnologies for the New Millennium 2007 Maspalomas, Gran Canaria, España: SPIE Digital Library. |
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