Ponencia
Programmable kernel analog VLSI convolution chip for real time vision processing
Autor/es | Serrano Gotarredona, María Teresa
Linares Barranco, Bernabé Andreou, Andreas G. |
Departamento | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores |
Fecha de publicación | 2000 |
Fecha de depósito | 2020-10-29 |
Publicado en |
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ISBN/ISSN | 0-7695-0619-4 1098-7576 |
Resumen | A neural architecture that implements a programmable 2D image filter has been presented. The architecture allows to implement any 2D filter F(p,q) decomposable into x-axis and y-axis components F(p,q) = H(p)V(q) such that ... A neural architecture that implements a programmable 2D image filter has been presented. The architecture allows to implement any 2D filter F(p,q) decomposable into x-axis and y-axis components F(p,q) = H(p)V(q) such that the product can be approximated by a signed minimum. Positive and negative values of H(p) and V(q) can be programmed. The architecture requires an address even representation (AER) input. This allows to rotate the 2D convolution kernel any angle. Circuit simulation results of critical components were given. System-level behavioral simulations of a 128x128 array have been included which validate the proposed approach. |
Cita | Serrano Gotarredona, M.T., Linares Barranco, B. y Andreou, A.G. (2000). Programmable kernel analog VLSI convolution chip for real time vision processing. En IJCNN 2000: IEEE-INNS-ENNS International Joint Conference on Neural Networks. Neural Computing: New Challenges and Perspectives for the New Millennium (62-65), Como, Italy: IEEE Computer Society. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Programmable Kernel Analog.pdf | 375.3Kb | [PDF] | Ver/ | |