dc.creator | Serrano Gotarredona, María Teresa | es |
dc.creator | Linares Barranco, Bernabé | es |
dc.date.accessioned | 2020-10-21T07:03:35Z | |
dc.date.available | 2020-10-21T07:03:35Z | |
dc.date.issued | 2012 | |
dc.identifier.citation | Serrano Gotarredona, M.T. y Linares Barranco, B. (2012). Design of adaptive nano/CMOS neural architectures. En ICECS 2012: 19th IEEE International Conference on Electronics, Circuits and Systems (949-952), Sevilla, España: IEEE Computer Society. | |
dc.identifier.isbn | 978-1-4673-1261-5 | es |
dc.identifier.uri | https://hdl.handle.net/11441/102098 | |
dc.description.abstract | Memristive devices are a promising technology to
implement dense learning synapse arrays emulating the high
memory capacity and connectivity of biological brains. Recently,
the implementation of STDP learning in memristive devices
connected to spiking neurons have been demonstrated as well as
the dependency of the form of the learning rule on the shape of
the applied spike. In this paper, we propose a fully CMOS
integrate-and-fire neuron generating a precisely shaped spike
that can be tuned through programmable biases. The
implementation of STDP learning is demonstrated through
electrical simulations of a 4x4 array of memristors connected to
4 spiking neurons. | es |
dc.description.sponsorship | Junta de Andalucía TIC-2010-6091 | es |
dc.description.sponsorship | Ministerio de Ciencia e Innovación TEC2009-10639-C04-01 | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad TEC2012-37868-C04-01 | es |
dc.description.sponsorship | European Union PRI-PIMCHI-2011-0768 | es |
dc.format | application/pdf | es |
dc.format.extent | 4 | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | ICECS 2012: 19th IEEE International Conference on Electronics, Circuits and Systems (2012), p 949-952 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Design of adaptive nano/CMOS neural architectures | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.relation.projectID | TIC-2010-6091 | es |
dc.relation.projectID | TEC2009-10639-C04-01 | es |
dc.relation.projectID | TEC2012-37868-C04-01 | es |
dc.relation.projectID | PRI-PIMCHI-2011-0768 | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/6463504 | es |
dc.identifier.doi | 10.1109/ICECS.2012.6463504 | es |
dc.publication.initialPage | 949 | es |
dc.publication.endPage | 952 | es |
dc.eventtitle | ICECS 2012: 19th IEEE International Conference on Electronics, Circuits and Systems | es |
dc.eventinstitution | Sevilla, España | es |
dc.relation.publicationplace | New York, USA | es |
dc.contributor.funder | Junta de Andalucía | es |
dc.contributor.funder | Ministerio de Ciencia e Innovación (MICIN). España | es |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España | es |
dc.contributor.funder | European Union (UE) | es |