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Listar por autor "Avedillo de Juan, María José"
Mostrando ítems 1-20 de 53
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Artículo
A CMOS-compatible oscillation-based VO2 Ising machine solver
Maher, Olivier; Jiménez, Manuel; Delacour, Corentin; Harnack, Nele; Núñez Martínez, Juan; Avedillo de Juan, María José; Linares Barranco, Bernabé; Todri Sanial, Aida; Indiveri, Giacomo; Karg, Siegfried (Springer Nature, 2024-04-18)Phase-encoded oscillating neural networks offer compelling advantages over metal-oxide-semiconductor-based technology for ...
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Artículo
A practical floating-gate Muller-C element using vMOS threshold gates
Rodríguez Villegas, Esther; Huertas Sánchez, Gloria; Avedillo de Juan, María José; Quintana Toledo, José María; Rueda Rueda, Adoración (Institute of Electrical and Electronics Engineers, 2001)This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on ...
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Tesis Doctoral
Algoritmos de codificación binaria de símbolos para la síntesis lógica de circuitos integrados digitales
Martínez Pérez, Manuel (2003-03-30) -
Tesis Doctoral
Una aproximación al diseño óptimo de máquinas de estados finitos
Avedillo de Juan, María José (1992-01-01)En los Capítulos 2 y 3 se aborda el diseño lógico FSMs. En el primero de ellos estudiamos el problema de la reducción del ...
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Ponencia
Assessing application areas for tunnel transistor technologies
Avedillo de Juan, María José; Núñez Martínez, Juan (Institute of Electrical and Electronics Engineers (IEEE), 2016)Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ...
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Ponencia
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits
Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Instituto Nacional de Astrofísica, Óptica y Electrónica; Universidad de Sevilla, 2012-03)The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an IV characteristic ...
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Artículo
Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas
Núñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2016)In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors ...
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Artículo
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
Núñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017)Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ...
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Ponencia
Complementary tunnel gate topology to reduce crosstalk effects
Núñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers (IEEE), 2017)Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome ...
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Artículo
COPAS: A New Algorithm for the Partial Input Encoding Problem
Martínez, Manuel; Avedillo de Juan, María José; Quintana Toledo, José María; Huertas Díaz, José Luis (Hindawi Publishing Corporation, 2002)Frequently, the logic designer deals with functions with symbolic input variables. The binary encoding of such symbols ...
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Tesis Doctoral
Desarrollo y evaluación de arquitecturas lógicas basadas en Nanopipeline.
Quintero Álvarez, Héctor Javier (2018-07-17)El potencial de la lógica dinámica, con sus fases de precarga y evaluación es una solución muy estudiada y aplicada, para ...
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Artículo
Digital Implementation of Oscillatory Neural Network for Image Recognition Applications
Abernot, Madeleine; Gil, Thierry; Jiménez, Manuel; Núñez Martínez, Juan; Avedillo de Juan, María José; Linares Barranco, Bernabé; Gonos, Théophile; Hardelin, Tanguy; Todri Sanial, Aida (Frontiers Media, 2021)Computing paradigm based on von Neuman architectures cannot keep up with the ever-increasing data growth (also called “data ...
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Trabajo Fin de Máster
Diseño de sistemas empotrados para aplicaciones de procesado de imagen y vídeo sobre FPGAs usando Vivado SDSoC
Pino Roldán, Roberto Joaquín del (2019-09)El procesado de imagen y vídeo es un campo que tiene una amplia área de aplicaciones, abarcando desde la automatización ...
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Trabajo Fin de Máster
Diseño de una red neuronal oscilatoria digital con capacidad de aprendizaje on-line sobre FPGA
Vázquez Díaz, Daniel (2023)La inteligencia artificial es un concepto que cada vez está más integrado en nuestras vidas. Aunque no nos demos cuenta, ...
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Tesis Doctoral
Diseño lógico de circuitos digitales usando dispositivos con característica NDR
Núñez Martínez, Juan (2011-02-04)En esta tesis doctoral se han desarrollado técnicas de diseño para circuitos electrónicos integrados que empleen dispositivos ...
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Ponencia
DOE based high-performance gate-level pipelines
Núñez Martínez, Juan; Avedillo de Juan, María José; Quintero Álvarez, Héctor Javier (Institute of Electrical and Electronics Engineers, 2014)Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in ...
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Artículo
Domino inspired MOBILE networks
Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2012)MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly ...
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Artículo
Effect of Device Mismatches in Differential Oscillatory Neural Networks
Shamsi, Jafar; Avedillo de Juan, María José; Linares Barranco, Bernabé; Serrano Gotarredona, María Teresa (IEEE, 2023-02)Analog implementation of Oscillatory Neural Networks (ONNs) has the potential to implement fast and ultra-low-power computing ...
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Artículo
Efficient realisation of MOS-NDR threshold logic gates
Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Wiley Open Access, 2009-11-05)A novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms ...
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Artículo
Efficient realization of a threshold voter for self-purging redundancy
Quintana Toledo, José María; Avedillo de Juan, María José; Huertas Díaz, José Luis (Springer, 2001)The self-purging technique is not commonly used mainly due to the lack of practical implementations of its key component, ...