Author profile: Bellido Díaz, Manuel Jesús
Institutional data
| Name | Bellido Díaz, Manuel Jesús |
| Department | Tecnología Electrónica |
| Knowledge area | Tecnología Electrónica |
| Professional category | Catedrático de Universidad |
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Statistics
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No. publications
81
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No. visits
9116
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No. downloads
15316
| Publications |
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Article
 IRIS: An embedded secure boot for IoT devices
(Elsevier, 2023)
This study proposes a hardware secure boot solution, an instant retrieval information system (IRIS) that is suitable for ... |
PhD Thesis
LILA (Low-level IoT Ligtweigth Applications): aplicaciones hardware para dispositivos IoT
(2022)
Esta tesis se enmarca dentro del Proyecto de Investigación TIN2017-89951-P: BootTimeIoT: Sistemas de inicio avanzados y ... |
Patent. Invention
Dispositivo electrónico calculador de funciones trigonométricas y usos del mismo
(Oficina Española de Patentes y Marcas (OEPM), 2021)
Dispositivo electrónico calculador de funciones trigonométricas y usos del mismo. En este documento se detalla un ... |
Article
Embedded LUKS (E-LUKS): A Hardware Solution to IoT Security
(MDPI, 2021)
The Internet of Things (IoT) security is one of the most important issues developers have to face. Data tampering must be ... |
Article
An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation
(IEEE Computer Society, 2021)
This paper introduces a design and on-chip verification framework for IPCores in FPGA platforms. The methodology of the ... |
Article
Using the complement of the cosine to compute trigonometric functions
(Springer, 2020)
The computation of the sine and cosine functions is required in devices ranging from application-specific signal processors ... |
Article
Address encoded byte order
(Elsevier B.V., 2020)
Unaligned accesses are forbidden in many high-performance architectures. In most of these architectures, the least significant ... |
Article
High-Performance Time Server Core for FPGA System-on-Chip
(MDPI, 2019)
This paper presents the complete design and implementation of a low-cost, low-footprint, network time protocol server core ... |
Patent. Invention
Circuito electrónico digital para el cálculo de senos y cosenos de múltiplos de un ángulo
(Oficina Española de Patentes y Marcas (OEPM), 2018)
Circuito electrónico pare el cálculo de los senos y cosenos de múltiplos de un ángulo que permite implementar eficientemente el cómputo de loe factores de twiddle de la transformada de Fourier. |
Article
Minimalistic SDHC-SPI hardware reader module for boot loader applications
(Elsevier, 2017)
This paper introduces a low-footprint full hardware boot loading solution for FPGA-based Programmable Systems on Chip. The ... |
Presentation
Metodología PBL en modo colaborativo aplicada al diseño de un SoC
(Universidad de Sevilla, 2016)
Dado el carácter principalmente práctico en las asignaturas de los másteres universitarios la metodología PBL es ampliamente ... |
Presentation
Building a basic membrane computer
(Fénix, 2016)
In this work, we present the building of two well-known membrane com- puters (squares generator and divisor test). Although ... |
Article
Fast Hardware Implementations of Static P Systems
(2016)
In this article we present a simulator of non-deterministic static P systems using Field Programmable Gate Array (FPGA) ... |
Presentation
evercodeML: a formal language for SoC integration
(IEEE Computer Society, 2015)
Complex SoC design devote a great part of the developing time to module integration tasks. The necessity of automating ... |
Article
NanoFS: a hardware-oriented file system
(IEEE Computer Society, 2013)
NanoFS is a novel file system for embedded systems and storage-class memories (like flash) and is specially designed to be ... |
Chapter of Book
Network Time Synchronization: A Full Hardware Approach
(Springer, 2012)
Complex digital systems are typically built on top of several abstraction levels: digital, RTL, computer, operating system ... |
Chapter of Book
Open Development Platform for Embedded Systems
(IntechOpen, 2012)
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| PhD Thesis |
Article
Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation
(IEEE Computer Society, 2011)
Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most ... |
Presentation
Python as a hardware description language: A case study
(IEEE Computer Society, 2011)
Many people may see the development of software and hardware like different disciplines. However, there are great similarities ... |
Presentation
Design and implementation of a suitable core for on-chip long-term verification
(IEEE Computer Society, 2010)
Traditional on-chip and off-chip logic analyzers present important shortcomings when used for the long-term verification ... |
Presentation
Delay and power consumption of static bulk-CMOS gates using independent bodies
(IEEE Computer Society, 2009)
Digital designs implemented using SOI processes employ separated bodies for each transistor. This approach is not usually ... |
Presentation
Efficient techniques and methodologies for embedded system design usign free hardware and open standards
(IEEE Computer Society, 2009)
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Presentation
Digital Data Processing Peripheral Design for an Embedded Application based on the Microblaze Soft Core
(IEEE Computer Society, 2008)
In this paper we present a design of a peripheral for MicroBlaze soft core processor as part of a R+D project carried out ... |
Presentation
La primera experiencia en el diseño de sistemas digitales sobre FPGAs
(Universidad Politécnica de Madrid, 2008)
Se presenta una práctica de introducción al diseño de sistemas digitales sobre FPGAs. El objetivo es que se pueda realizar ... |
Chapter of Book
Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates
(Springer, 2008)
Power modeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of static ... |
| PhD Thesis |
Presentation
Implementation of a FFT/IFFT Module on FPGA: Comparison of Methodologies
(IEEE Computer Society, 2008)
In this work, we have compared three different methodologies for the implementation of a FFT/IFFT module on FPGA: VHDL ... |
Presentation
Design and Implementation of a SNTP Client on FPGA
(IEEE Computer Society, 2008)
This contribution presents the design and implementation of a SNTP client module suitable for IEC 61850 environments fully ... |
Presentation
Building a SoC for industrial applications based on LEON microprocessor and a GNU/Linux distribution
(IEEE Computer Society, 2008)
This paper presents the design of a complete RTU (Remote Terminal Unit) with a System-on-Chip solution based completely ... |
PhD Thesis
Simulación lógica temporal de altas prestaciones y aplicación a la estimación del consumo de potencia y corriente en circuitos integrados CMOS-VLSI
(2007)
El primer capítulo está dedicado a la simulación y verificación temporal de circuitos VLSI en general, así como a los ... |
Presentation
Design of a FFT/IFFT module as an IP core suitable for embedded systems
(IEEE Computer Society, 2007)
In this work, we have laid the foundations that allow us to accomplish the implementation of a FFT/IFFT module as an IP ... |
Chapter of Book
Static Power Consumption in CMOS Gates Using Independent Bodies
(Springer, 2007)
It has been reported that the use of independent body terminals for series transistors in static bulk-CMOS gates improves ... |
Presentation
Automatic logic synthesis for parallel alternating latches clocking schemes
(SPIE Digital Library, 2007)
This paper proposes a VHDL coding technique that allows for the automatic synthesis of digital circuits using the so called ... |
Presentation
A SoC Design Methodology for LEON2 on FPGA
(IBERCHIP, 2006)
SoC design methodologies show up as a natural and productive method to implement embedded and/or ubiquitous systems. The ... |
Presentation
Diseño e implantación de SoPC basados en el microprocesador PicoBlaze
(Universidad Politécnica de Madrid, 2006)
Con este trabajo pretendemos realizar una aportación a la docencia de la materias que cu bren el diseño de SoPC (System ... |
Presentation
Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements
(IEEE Computer Society, 2006)
This contribution successfully accomplished the design and implementation of an advanced DSP circuit for direct measurements ... |
Presentation
Diseño e Implementación Óptima de Periféricos de DSP con System Generator para Microblaze
(IBERCHIP, 2006)
Con este trabajo pretendemos analizar como se lleva a cabo el diseño de periféricos de DSP utilizando uno de los nuevos ... |
Presentation
Desarrollo en VHDL de un filtro digital genérico basado en estructuras canónicas.
(Universidad Politécnica de Madrid, 2006)
Este trabajo abarca la realización de un filtro digital a bajo nivel. El diseño propuesto se basa en la utilización de un ... |
Article
Automated performance evaluation of skew-tolerant clocking schemes
(Taylor and Francis Online, 2006)
In this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes ... |
Presentation
Diseño e implementación de SOPC basados en el microprocesador Picoblaze
(Universidad Politécnica de Madrid, 2006)
Con este trabajo pretendemos realizar una aportación a la docencia de la materias que cubren el diseño de SoPC (System on ... |
Presentation
Optimization techniques for dynamic behavior modeling of digital CMOS VLSI circuits in nanometric technologies
(IEEE Computer Society, 2005)
In the field of logic simulation, the constant advance of technology influences remarkably in the circuits dynamic behavior. ... |
Presentation
Efficient Design of a FFT/IFFT-64 Module on ASIC
(IBERCHIP, 2005)
In this work we present the VHDL implementation of a FFT/IFFT-64 module. This implementation: (a) is relatively quick and ... |
Article
Application of Internode model to global power consumption estimation in SCMOS gates
(Springer, 2005)
In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based ... |
Presentation
Algorithms to get the maximum operation frequency for skew-tolerant clocking schemes
(Society of Photo-Optical Instrumentation Engineers (SPIE), 2005)
Nowadays it is not possible to neglect the delay of interconnection lines. The die size is rising very fast, and the delay ... |
Chapter of Book
Logic-Level Fast Current Simulation for Digital CMOS Circuits
(Springer, 2005)
Nowadays, verification of digital integrated circuit has been focused more and more from the timing and area field to ... |
Presentation
Análisis del comportamiento de la videoconsola Atari 2600 como sistema digital real basado en microprocesador en el laboratorio de electrónica.
(Universidad Politécnica de Valencia, 2004)
En este trabajo se propone una práctica de laboratorio para la asignatura Estructura de Computadores de primer curso de ... |
Article
Signal Sampling Based Transition Modeling for Digital Gates Characterization
(Springer, 2004)
Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel ... |
Presentation
ADKI: un sistema web de adquisición de datos bajo Linux
(Universidad Politécnica de Valencia, 2004)
Esta contribución presenta una aplicación genérica de adquisición de datos y control para sistemas simples que incorpora ... |
Presentation
Modelos de adaptación de los programas formativos al espacio europeo
(Universidad Politécnica de Valencia, 2004)
Ante el volumen de información a veces contradictoria acerca de la educación, en este artículo pretendemos presentar una ... |
Presentation
Seguridad en Internet: web spoofing
(Universidad Politécnica de Valencia, 2004)
En este trabajo se estudia la técnica Web Spoofing como método de ataque a través de Internet. Se trata de una variante ... |
Presentation
Diseño del microcontrolador 8051 con módulo ensamblador- generador de ROM en lenguaje VHDL
(Universidad Politécnica de Valencia, 2004)
En este trabajo se presenta el resultado de un Proyecto Fin de Carrera en el que se ha diseñado el microcontrlador 8051 ... |
Presentation
Internode: Internal Node Logic Computational Model
(IEEE Computer Society, 2003)
In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational ... |
Article
Aprendizaje interdisciplinar de la electrónica y las comunicaciones
(Universidad de Sevilla: Instituto de Ciencias de la Educación, 2003)
En este proyecto de innovación docente se pretende profundizar en el conocimiento de la base teórica, la construcción de ... |
Chapter of Book
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits
(Springer, 2003)
The verification of the timing requirements of large VLSI circuits is generally performed by using simulation or timing ... |
Article
Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)
(Springer, 2002)
In previous papers we have presented a very accurate model that handles the generation and propagation of glitches, which ... |
Chapter of Book
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level
(Springer, 2002)
Accurate estimation of switching activity is very important in digital circuits. In this paper we present a comparison ... |
Chapter of Book
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level
(Springer, 2002)
This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current ... |
Presentation
AUTODDM: AUTOmatic characterization tool for the Delay Degradation Model
(IEEE Computer Society, 2001)
As delay models used in logic timing simulation become more and more complex, the problem of model parameter values ... |
Presentation
Gate-Level Simulation of CMOS Circuits Using the IDDM Model
(IEEE Computer Society, 2001)
Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the ... |
Presentation
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model
(IEEE Computer Society, 2001)
This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation ... |
PhD Thesis
Degradación del retraso de propagación en puertas lógicas CMOS VLSI
(2000)
La evolución en la tecnología de circuitos VLSI da lugar, entre otras cosas, a un aumento en la escala de integración ... |
Presentation
Inertial and Degradation Delay Model for CMOS Logic Gates
(IEEE Computer Society, 2000)
The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the ... |
Chapter of Book
Degradation Delay Model Extension to CMOS Gates
(Springer, 2000)
This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic ... |
Chapter of Book
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits
(Springer, 2000)
This communication shows the influence of clocking schemes on the digital switching noise generation. It will be shown how ... |
Presentation
Concepción de un microprocesador: de la especificación a la realización
(Universidad Politécnica de Madrid, 2000)
|
Presentation
Un entorno informático de ayuda a la docencia de sistemas de comunicación optoelectrónicos
(Universidad Politécnica de Madrid, 2000)
|
Article
Aprendiendo a diseñar circuitos integrados digitales mediante el uso del ordenador
(Universidad de Sevilla, 1999)
En este trabajo se presenta una experiencia docente encaminada a mejorar la asimilación por parte de los alumnos de algunos ... |
Presentation
Realización de un Sistema Digital: implementación sobre FPGA y testado en Laboratorio
(Universidad Politécnica de Madrid, 1998)
|
Presentation
Delay degradation effect in submicronic CMOS inverters
(Université Catholique de Louvain, 1997)
This communication presents the evidence of a degradation effect causing important reductions in the delay of a CMOS ... |
Article
Analysis of Metastable Operation in a CMOS Dynamic D-Latch
(Springer, 1997)
Nowadays, metastability is becoming a serious problem in high-performance VLSI design, mainly due to the relatively-high ... |
Presentation
Sistema multimedia móvil aplicado a la enseñanza de la electrónica
(Universidad de Sevilla, 1996)
|
Presentation
New CMOS VLSI Linear Self-Timed Architectures
(1995)
The implementation of digital signal processor circuits via self-timed techniques is currently a valid altemative to solve ... |
Presentation
Sistemas multimedia de enseñanza aprendizaje de la electrónica
(Universitat de Barcelona, 1995)
En un mundo complejo y cambiante como el nuestro, a veces resulta difícil comprender en profundidad los avances que vivimos ... |
Presentation
Enseñanza integrada: Una aplicación a la docencia de circuitos secuenciales
(Universidad Politécnica de Madrid, 1994)
|
Presentation
Aplicación del VHDL en prácticas de diseño de sistemas digitales
(Universidad Politécnica de Madrid, 1994)
|
| PhD Thesis |
Presentation
Modeling of Real Bistables in VHDL
(IEEE Computer Society, 1993)
A complete VHDL model of bistables including their metastable operation is presented. An RS-NAND latch has been modelled ... |
Presentation
Arquitectura para el diseño de circuitos autotemporizados bidimensionales. Realización de multiplicadores
(Universidad de Málaga, 1993)
La realización de sistemas digitales mediante técnicas autotemporizadas constituye la mejor alternativa para resolver la ... |
Presentation
Un nuevo modelo de retraso para puertas lógicas CMOS
(Universidad de Málaga, 1993)
Los modelos de retraso para puertas lógicas, que usan la mayoría de los simuladores lógicos, carecen de la suficiente ... |
Presentation
Determinación del coeficiente de resolución en biestables RS CMOS
(Universidad Politécnica de Madrid. Laboratorio de Sistemas Integrados, 1992)
El diseño de biestables con riesgo de metaestabilidad requiere que posean coeficientes de resolución adecuados. En este ... |
