Author profile: Ginés Arteaga, Antonio José
Institutional data
Name | Ginés Arteaga, Antonio José |
Department | Electrónica y Electromagnetismo |
Knowledge area | Electrónica |
Professional category | Profesor Contratado Doctor |
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Statistics
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No. publications
15
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No. visits
1385
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No. downloads
3486
Publications |
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Final Degree Project |
Final Degree Project |
Final Degree Project |
Presentation
On-chip Reduced-code Static Linearity Test of Vcm-based Switching SAR ADCs Using an Incremental Analog-to-digital Converter
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
This paper describes a BIST technique for the static linearity test of Vcm-based successive-approximation analog-to-digital ... |
Presentation
Static Linearity BIST for Vcm-based Switching SAR ADCs Using a Reduced-code Measurement Technique
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
This work presents a reduced-code strategy for the static linearity self-testing of Vcm -based successive-approximation ... |
Master's Final Project |
Article
Design methodology for low-jitter differential clock recovery circuits in high performance ADCs
(Springer, 2016)
This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low ... |
Presentation
A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications
(Institute of Electrical and Electronics Engineers, 2016)
This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical ... |
Article
Background Digital Calibration of Comparator Offsets in Pipeline ADCs
(Institute of Electrical and Electronics Engineers, 2015)
This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital ... |
Article
Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators
(Institute of Electrical and Electronics Engineers, 2014)
This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed ... |
Patent
Procedimiento adaptativo de calibración dígital concurrente del offset en comparadores en convertidores analógico-digitales (adcs).
(Oficina Española de Patentes y Marcas , 2012)
El objeto de la presente invención es un procedimiento adaptativo para la calibración del offset de comparadores en ... |
Patent
Procedimiento adaptativo para la estimación de la inl en convertidores analógico-digitales (adcs).
(Oficina Española de Patentes y Marcas , 2012)
Procedimiento adaptativo para la estimación de la INL en convertidores analógico-digitales (ADCs).Permite caracterizar y ... |
Article
On chopper effects in discrete-time ΣΔ modulators
(Institute of Electrical and Electronics Engineers, 2010)
Analog-to-digital converters based on ΣΔ modulators are used in a wide variety of applications. Due to their inherent ... |
Presentation
Random chopping in ΣΔ modulators
(2009)
Σ∆ modulators make a clever use of oversampling and exhibit inherent monotonicity, high linearity and large dynamic range ... |
Presentation
A 2.5MHz bandpass active complex filter With 2.4MHz bandwidth for wireless communications
(2008)
This paper presents a fully differential 8thorder transconductor-based active complex filter with 2.4MHz bandwidth and ... |