Perfil del autor: Espejo Meana, Servando Carlos
Datos institucionales
| Nombre | Espejo Meana, Servando Carlos |
| Departamento | Electrónica y Electromagnetismo |
| Área de conocimiento | Electrónica |
| Categoría profesional | Profesor Titular de Universidad |
| Correo electrónico | Solicitar |
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Estadísticas
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Nº publicaciones
58
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Nº visitas
4523
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Nº descargas
5412
| Publicaciones |
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Artículo
 The Uranus Multi-Experiment Radiometer for Haze and Clouds Characterization
(Springer Nature, 2024)
The aerosols (clouds and hazes) on Uranus are one of the main elements for understanding the thermal structure and dynamics ... |
Artículo
The Diverse Meteorology of Jezero Crater over the First 250 Sols of Perseverance on Mars
(Springer Nature, 2023)
NASA’s Perseverance rover’s Mars Environmental Dynamics Analyzer is collecting data at Jezero crater, characterizing the ... |
Tesis Doctoral
Diseño CMOS de sistemas de front-end para instrumentación ambiental en Marte
(2016)
En este trabajo de tesis se presenta el diseño y proceso de cualificación para espacio del ASIC de señal mixta que integrará ... |
Artículo
A Front-End ASIC for a 3-D Magnetometer for Space Applications by Using Anisotropic Magnetoresistors
(Institute of Electrical and Electronics Engineers, 2015)
This paper presents an application-specific integrated circuit (ASIC) aimed for an alternative design of a digital 3-D ... |
Artículo
Four-channel self-compensating single-slope ADC for space environments
(Institution of Electrical Engineers, 2014)
A multichannel high-resolution single-slope analogue-to-digital converter (SS ADC) is presented that automatically compensates ... |
Ponencia
OWLs: A mixed-signal ASIC for optical wire-less links in space instruments
(European Space Agency. Publications Division, 2012)
This paper describes the design of a mixed-signal ASIC for space application and the techniques employed for radiation ... |
Ponencia
ACE 16k based stand-alone system for real-time pre-processing tasks
(The International Society for Optical Engineering - SPIE, 2005)
This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's ... |
Artículo
A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
(Institute of Electrical and Electronics Engineers, 2004)
This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of ... |
Artículo
Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS
(Institute of Electrical and Electronics Engineers, 2004)
Based on studies of the mammalian retina, a bioinspired model for mixed-signal array processing has been implemented on ... |
Artículo
ACE16K: The Third Generation of Mixed-Signal SIMD-CNN ACE Chips Toward VSoCs
(Institute of Electrical and Electronics Engineers, 2004)
Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible ... |
Ponencia
A mixed-signal early vision chip with embedded image and programming memories and digital I/O
(The International Society for Optical Engineering - SPIE, 2003)
From a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable ... |
Ponencia
Analog weight buffering strategy for CNN chips
(Institute of Electrical and Electronics Engineers, 2003)
Large, gray-scale CNN chips employ analog signals to achieve high-density in the internal distribution of the template ... |
Artículo
A Bio-Inspired Two-Layer Mixed-Signal Flexible Programmable Chip for Early Vision
(Institute of Electrical and Electronics Engineers, 2003)
A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has ... |
Ponencia
A versatile sensor interface for programmable vision systems-on-chip
(The International Society for Optical Engineering - SPIE, 2003)
This paper describes an optical sensor interface designed for a programmable mixed-signal vision chip. This chip has been ... |
Ponencia
Programmable retinal dynamics in a CMOS mixed-signal array processor chip
(The International Society for Optical Engineering - SPIE, 2003)
The low-level image processing that takes place in the retina is intended to compress the relevant visual information to ... |
Ponencia
Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics
(Institute of Electrical and Electronics Engineers, 2002)
A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the ... |
Ponencia
Mismatch-induced tradeoffs and scalability of mixed-signal vision chips
(Institute of Electrical and Electronics Engineers, 2002)
This paper explores different trade-offs associated with the design of analog VLSI chips. These trade-offs are related to ... |
Ponencia
A processing element architecture for high-density focal plane analog programmable array processors
(Institute of Electrical and Electronics Engineers, 2002)
The architecture of the elementary Processing Element - PE- used in a recently designed 128×128 Focal Plane Analog ... |
Ponencia
A multimode gray-scale CMOS optical sensor for visual computers
(Institute of Electrical and Electronics Engineers, 2002)
This paper presents a new multimode optical sensor architecture for the optical interface of Visual CNN (cellular neural ... |
Ponencia
CMOS realization of a 2-layer CNN universal machine chip
(Institute of Electrical and Electronics Engineers, 2002)
Some of the features of the biological retina can be modelled by a cellular neural network (CNN) composed of two dynamically ... |
Ponencia
ACE16K: A 128×128 focal plane analog processor with digital I/O
(Institute of Electrical and Electronics Engineers, 2002)
This paper presents a new generation 128×128 focal-plane analog programmable array processor (FPAPAP), from a system level ... |
Ponencia
ACE16k: A programmable focal plane vision processor with 128 x 128 resolution
(European Conference on Circuit Theory and Design, 2001)
This paper presents a new generation 128x128 Focal Plane Analog Programmable Array Processor (FPAPAP), from a system ... |
Ponencia
Structure reconfigurability of the CNNUC3 for robust template operation
(Institute of Electrical and Electronics Engineers, 2000)
We demonstrate the importance of the reconfigurability of a 64/spl times/64 cells size CNN-UM chip. As we show, in such a ... |
Ponencia
Object oriented image segmentation on the CNNUC3 chip
(Institute of Electrical and Electronics Engineers, 2000)
We show how a complex object oriented image analysis algorithm can be implemented on a CNNUM chip for video-coding. Besides ... |
Ponencia
Experimental demonstration of real-time image-processing using a VLSI analog programmable array processor
(SPIE- The International Society for Optical Engineering, 2000)
This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitallyprogrammable analog ... |
Ponencia
Implementation of non-linear templates using a decomposition technique by a 0.5 /spl mu/m CMOS CNN universal chip
(Institute of Electrical and Electronics Engineers, 2000)
This paper demonstrates the processing capabilities of a recently designed analog programmable array processor. This new ... |
Ponencia
CNN technology in action
(Institute of Electrical and Electronics Engineers, 2000)
Two Cellular Neural Net Universal Machine (CNN-UM) prototypes are demonstrated in action. The first one is the latest 4096 ... |
Ponencia
Realization of non-linear templates using the CNNUC3 prototype
(Institute of Electrical and Electronics Engineers, 2000)
Demonstrates the processing capabilities of an analog programmable array processor chipMINUS/CNNUC3-which follows the ... |
Ponencia
Programmable resolution imager for imaging applications
(SPIE- The International Society for Optical Engineering, 2000)
In this paper a programmable imager with averaging capabilities will be described which is intended for averaging of ... |
Ponencia
The CNNUC3: an analog I/O 64x64 CNN universal machine chip prototype with 7-bit analog accuracy
(Institute of Electrical and Electronics Engineers, 2000)
This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitally-programmable ... |
Artículo
SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips
(Wiley-Blackwell, 1999)
This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing ... |
Artículo
An 0.5-μm CMOS analog random access memory chip for TeraOPS speed multimedia video processing
(Institute of Electrical and Electronics Engineers, 1999)
Data compressing, data coding, and communications in object-oriented multimedia applications like telepresence, computer-aided ... |
Ponencia
Challenges in mixed-signal IC design of CNN chips in submicron CMOS
(Institute of Electrical and Electronics Engineers, 1998)
Summary form only given. The contrast observed between the performance of artificial vision machines and "natural" vision ... |
Ponencia
Four-quadrant one-transistor-synapse for high-density CNN implementations
(Institute of Electrical and Electronics Engineers, 1998)
Presents a linear four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation ... |
Artículo
Electrooptical measurement system for the DC characterization of visible detectors for CMOS-compatible vision chips
(IEEE, 1998)
Abstract—An electrooptical measurement system for the dc characterization of visible detectors for CMOS-compatible ... |
Ponencia
A 0.5 /spl mu/m CMOS CNN analog random access memory chip for massive image processing
(Institute of Electrical and Electronics Engineers, 1998)
An analog RAM has been designed to act as a cache memory for a CNN Universal Machine. Hence, all the non-standard chips ... |
Artículo
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
(Institute of Electrical and Electronics Engineers, 1997)
This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) ... |
Ponencia
Design of a programmable mixed-signal CMOS image-processing chip in 0.8 /spl mu/m CMOS
(Institute of Electrical and Electronics Engineers, 1997)
An operational vision-chip prototype with a wide-range of potential applications in artificial-vision systems is presented. ... |
Ponencia
Some design trade-offs for large CNN chips using small-size transistors
(Institute of Electrical and Electronics Engineers, 1997)
Small-size MOS transistors (MOST) exhibit a bunch of second-order effects which limit their application to design Cellular ... |
Ponencia
A one-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors
(Institute of Electrical and Electronics Engineers, 1997)
This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the ... |
Ponencia
Hybrid-control of synapse circuits for programmable cellular neural networks
(Institute of Electrical and Electronics Engineers, 1996)
This paper describes a hybrid weight-control strategy for VLSI realizations of programmable Cellular Neural Networks (CNNs), ... |
Ponencia
Mixed-signal CNN array chips for image processing
(The International Society for Optical Engineering, 1996)
Due to their local connectivity and wide functional capabilities, cellular nonlinear networks (CNN) are excellent candidates ... |
Ponencia
Realization of a CNN universal chip in CMOS technology
(Institute of Electrical and Electronics Engineers, 1995)
This paper describes the design of a programmable Cellular Neural Network (CNN) chip, with additional functionalities ... |
Tesis Doctoral
Redes neuronales celulares: modelado y diseño monolítico
(1994)
Las aportaciones principales de esta Tesis se refieren al diseño de circuitos electrónicos con las primitivas disponibles ... |
Ponencia
Convergence and stability of the FSR CNN model
(Institute of Electrical and Electronics Engineers, 1994)
Stability and convergency results are reported for a modified continuous-time CNN model. The signal range of the state ... |
Ponencia
A countinuous-time cellular neural network chip for direction-selectable connected component detection with optical image acquisition
(Institute of Electrical and Electronics Engineers, 1994)
This paper presents a continuous-time Cellular Neural Network (CNN) chip [1] for the application of Connected Component ... |
Ponencia
SIRENA: A simulation environment for CNNs
(Institute of Electrical and Electronics Engineers, 1994)
SIRENA is a general simulation environment for artificial neural networks, with emphasis towards CNNs. A special interest ... |
Ponencia
CNN universal chip in CMOS technology
(Institute of Electrical and Electronics Engineers, 1994)
This paper describes the design of a CNN universal chip in a standard CMOS technology. The core of the chip consists of ... |
Artículo
CMOS optical-sensor array with high output current levels and automatic signal-range centring
(Institution of Engineering and Technology, 1994)
A CMOS compatible photosensor with high output current levels, and an area-efficient scheme for automatic signal-range ... |
Ponencia
Weight-control strategy for programmable CNN chips
(Institute of Electrical and Electronics Engineers, 1994)
This paper describes a hybrid weight-control strategy for the VLSI realization of programmable CNNs, based on automatic ... |
Artículo
Smart-Pixel Cellular Neural Networks in Analog Current-Mode CMOS Technology
(Institute of Electrical and Electronics Engineers, 1994)
This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. ... |
Artículo
Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks
(Institute of Electrical and Electronics Engineers, 1993)
This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular ... |
Ponencia
A Model for VLSI implementation of CNN image processing chips using current-mode techniques
(Institute of Electrical and Electronics Engineers, 1993)
A new Cellular Neural Network model is proposed which allows simpler and faster VLSI implementation than previous models. ... |
Artículo
A Chaotic Switched-Capacitor Circuit for 1/f Noise Generation
(Institute of Electrical and Electronics Engineers, 1992)
A switched-capacitor circuit is reported for the generation of 1 / fYnoise. The circuit is described by a chaotic first-order ... |
Ponencia
Switched-current techniques for image processing Cellular Neural Networks in MOS VLSI
(Institute of Electrical and Electronics Engineers, 1992)
An architecture and related building blocks are presented for the realization of image processing tasks using current-mode ... |
Artículo
A switched-capacitor broadband noise generator for CMOS VLSI
(Institution of Engineering and Technology, 1991)
A switched-capacitor circuit is reported for the generation of broadband white noise in MOS VLSI. It is based on the ... |
Ponencia
Design of an analog/digital truly random number generator
(Institute of Electrical and Electronics Engineers, 1990)
An analog-digital system is presented for the generation of truly random (aperiodic) digital sequences. This model is based ... |
Ponencia
Application of piecewise-linear switched-capacitor circuits for random number generation
(Institute of Electrical and Electronics Engineers, 1989)
An unconventional application of switched-capacitor (SC) circuits is discussed. A systematic method for the design of ... |