dc.creator | Río Fernández, Rocío del | es |
dc.creator | Medeiro Hidalgo, Fernando | es |
dc.creator | Pérez Verdú, Belén | es |
dc.creator | Rodríguez Vázquez, Ángel Benito | es |
dc.date.accessioned | 2019-10-10T17:00:55Z | |
dc.date.available | 2019-10-10T17:00:55Z | |
dc.date.issued | 2000 | |
dc.identifier.citation | Río Fernández, R.d., Medeiro Hidalgo, F., Pérez Verdú, B. y Rodríguez Vázquez, Á.B. (2000). Reliable analysis of settling errors in SC integrators-application to the design of high-speed /spl Sigma//spl Delta/ modulators. En 2000 IEEE International Symposium on Circuits and Systems (ISCAS) (IV-417-IV-420), Ginebra, Suiza: Institute of Electrical and Electronics Engineers. | |
dc.identifier.isbn | 0-7803-5482-6 | es |
dc.identifier.uri | https://hdl.handle.net/11441/89604 | |
dc.description.abstract | This paper presents a detailed study on the transient response of SC integrators which takes into account the effects of amplifier finite gain-bandwidth product, slew-rate, and parasitic capacitances. Unlike previous models, both the integration and the sampling phases are considered. Experimental measurements of the settling error power of a 2nd-order /spl Sigma//spl Delta/ modulator are used to validate the model. When compared to previous models, the new one provides more reliable estimations of the defective settling in optimized high-speed /spl Sigma//spl Delta/ modulators. The results in the paper show up to -16 dB difference in the estimation of the in-band error power of a 2-1-1 mb /spl Sigma//spl Delta/M intended for 14 bit@4 M Samples/s. | es |
dc.description.sponsorship | European Commission 29261 | es |
dc.description.sponsorship | Comisión Interministerial de Ciencia y Tecnología TIC 97-0580 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | 2000 IEEE International Symposium on Circuits and Systems (ISCAS) (2000), p IV-417-IV-420 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.title | Reliable analysis of settling errors in SC integrators-application to the design of high-speed /spl Sigma//spl Delta/ modulators | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | 29261 | es |
dc.relation.projectID | TIC 97-0580 | es |
dc.relation.publisherversion | https://doi.org/10.1109/ISCAS.2000.858777 | es |
dc.identifier.doi | 10.1109/ISCAS.2000.858777 | es |
idus.format.extent | 4 p. | es |
dc.publication.initialPage | IV-417 | es |
dc.publication.endPage | IV-420 | es |
dc.eventtitle | 2000 IEEE International Symposium on Circuits and Systems (ISCAS) | es |
dc.eventinstitution | Ginebra, Suiza | es |
dc.identifier.sisius | 5402122 | es |