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Multi-bit cascade ΣΔ modulator for high-speed A/D conversion with reduced sensitivity to DAC errors

 

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Opened Access Multi-bit cascade ΣΔ modulator for high-speed A/D conversion with reduced sensitivity to DAC errors
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Author: Medeiro Hidalgo, Fernando
Pérez Verdú, Belén
Rosa Utrera, José Manuel de la
Rodríguez Vázquez, Ángel Benito
Department: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Date: 1998
Published in: Electronics Letters, 34 (5), 422-424.
Document type: Article
Abstract: This paper presents a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantization in a cascade architecture to obtain high resolution with low oversampling ratio. It is less sensitive to the non-linearity of the DAC than those previously reported, thus enabling the use of very simple analog circuitry with neither calibration nor trimming required.
Cite: Medeiro Hidalgo, F., Pérez Verdú, B., Rosa Utrera, J.M.d.l. y Rodríguez Vázquez, Á.B. (1998). Multi-bit cascade ΣΔ modulator for high-speed A/D conversion with reduced sensitivity to DAC errors. Electronics Letters, 34 (5), 422-424.
Size: 1.126Mb
Format: PDF

URI: https://hdl.handle.net/11441/77558

DOI: 10.1049/el:19980270

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