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dc.creatorGuerrero Martos, Davides
dc.creatorBellido Díaz, Manuel Jesúses
dc.creatorJuan Chico, Jorgees
dc.creatorMillán Calderón, Alejandroes
dc.creatorRuiz de Clavijo Vázquez, Paulinoes
dc.creatorOstúa Arangüena, Enriquees
dc.creatorViejo Cortés, Juliánes
dc.date.accessioned2018-07-24T08:56:48Z
dc.date.available2018-07-24T08:56:48Z
dc.date.issued2006
dc.identifier.citationGuerrero Martos, D., Bellido Díaz, M.J., Juan Chico, J., Millán Calderón, A., Ruiz de Clavijo Vázquez, P., Ostúa Arangüena, E. y Viejo Cortés, J. (2006). Automated performance evaluation of skew-tolerant clocking schemes. International Journal of Electronics, 93 (12), 819-842.
dc.identifier.issn0020-7217es
dc.identifier.urihttps://hdl.handle.net/11441/77541
dc.description.abstractIn this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes are the well known master–slave clocking scheme (MS) and two schemes developed by the authors: Parallel alternating latches clocking scheme (PALACS) and four-phase parallel alternating latches clocking scheme (four-phase PALACS). In order to evaluate the timing performance, the authors introduce algorithms to obtain the clock waveforms required by a synchronous sequential circuit. Separated algorithms were developed for every clocking scheme. From these waveforms it is possible to get parameters such as the non-overlapping time and the clock period. They have been implemented in a tool and have been used to compare the timing performance of the clocking schemes applied to a simple circuit. To analyse the power consumption the authors have electrically simulated a simple circuit for several operation frequencies. The most remarkable conclusion is that it is possible to save about 50% of the power consumption of the clock distribution network by using PALACS.es
dc.description.sponsorshipMinisterio de Ciencia y Tecnología TEC 2004-00840/MICes
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherTaylor and Francis Onlinees
dc.relation.ispartofInternational Journal of Electronics, 93 (12), 819-842.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectClock skew tolerancees
dc.subjectHigh speed CMOS designes
dc.subjectLow poweres
dc.titleAutomated performance evaluation of skew-tolerant clocking schemeses
dc.typeinfo:eu-repo/semantics/articlees
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/submittedVersiones
dc.rights.accessrightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Tecnología Electrónicaes
dc.relation.projectIDTEC 2004-00840/MICes
dc.relation.publisherversionhttps://www.tandfonline.com/doi/full/10.1080/00207210500347410es
dc.identifier.doi10.1080/00207210500347410es
idus.format.extent24es
dc.journaltitleInternational Journal of Electronicses
dc.publication.volumen93es
dc.publication.issue12es
dc.publication.initialPage819es
dc.publication.endPage842es
dc.identifier.sisius6701462es
dc.contributor.funderMinisterio de Ciencia y Tecnología (MCYT). España

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