dc.creator | Guerrero Martos, David | es |
dc.creator | Bellido Díaz, Manuel Jesús | es |
dc.creator | Juan Chico, Jorge | es |
dc.creator | Millán Calderón, Alejandro | es |
dc.creator | Ruiz de Clavijo Vázquez, Paulino | es |
dc.creator | Ostúa Arangüena, Enrique | es |
dc.creator | Viejo Cortés, Julián | es |
dc.date.accessioned | 2018-07-24T08:56:48Z | |
dc.date.available | 2018-07-24T08:56:48Z | |
dc.date.issued | 2006 | |
dc.identifier.citation | Guerrero Martos, D., Bellido Díaz, M.J., Juan Chico, J., Millán Calderón, A., Ruiz de Clavijo Vázquez, P., Ostúa Arangüena, E. y Viejo Cortés, J. (2006). Automated performance evaluation of skew-tolerant clocking schemes. International Journal of Electronics, 93 (12), 819-842. | |
dc.identifier.issn | 0020-7217 | es |
dc.identifier.uri | https://hdl.handle.net/11441/77541 | |
dc.description.abstract | In this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes are the well known master–slave clocking scheme (MS) and two schemes developed by the authors: Parallel alternating latches clocking scheme (PALACS) and four-phase parallel alternating latches clocking scheme (four-phase PALACS). In order to evaluate the timing performance, the authors introduce algorithms to obtain the clock waveforms required by a synchronous sequential circuit. Separated algorithms were developed for every clocking scheme. From these waveforms it is possible to get parameters such as the non-overlapping time and the clock period. They have been implemented in a tool and have been used to compare the timing performance of the clocking schemes applied to a simple circuit. To analyse the power consumption the authors have electrically simulated a simple circuit for several operation frequencies. The most remarkable conclusion is that it is possible to save about 50% of the power consumption of the clock distribution network by using PALACS. | es |
dc.description.sponsorship | Ministerio de Ciencia y Tecnología TEC 2004-00840/MIC | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Taylor and Francis Online | es |
dc.relation.ispartof | International Journal of Electronics, 93 (12), 819-842. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Clock skew tolerance | es |
dc.subject | High speed CMOS design | es |
dc.subject | Low power | es |
dc.title | Automated performance evaluation of skew-tolerant clocking schemes | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessrights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.projectID | TEC 2004-00840/MIC | es |
dc.relation.publisherversion | https://www.tandfonline.com/doi/full/10.1080/00207210500347410 | es |
dc.identifier.doi | 10.1080/00207210500347410 | es |
idus.format.extent | 24 | es |
dc.journaltitle | International Journal of Electronics | es |
dc.publication.volumen | 93 | es |
dc.publication.issue | 12 | es |
dc.publication.initialPage | 819 | es |
dc.publication.endPage | 842 | es |
dc.identifier.sisius | 6701462 | es |
dc.contributor.funder | Ministerio de Ciencia y Tecnología (MCYT). España | |