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Automated performance evaluation of skew-tolerant clocking schemes

 

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Opened Access Automated performance evaluation of skew-tolerant clocking schemes
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Author: Guerrero Martos, David
Bellido Díaz, Manuel Jesús
Juan Chico, Jorge
Millán Calderón, Alejandro
Ruiz de Clavijo Vázquez, Paulino
Ostúa Aranguena, Enrique
Viejo Cortés, Julián
Department: Universidad de Sevilla. Departamento de Tecnología Electrónica
Date: 2006
Published in: International Journal of Electronics, 93 (12), 819-842.
Document type: Article
Abstract: In this paper the authors evaluate the timing and power performance of three skew-tolerant clocking schemes. These schemes are the well known master–slave clocking scheme (MS) and two schemes developed by the authors: Parallel alternating latches cl...
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Cite: Guerrero Martos, D., Bellido Díaz, M.J., Juan Chico, J., Millán Calderón, A., Ruiz de Clavijo Vázquez, P., Ostúa Aranguena, E. y Viejo Cortés, J. (2006). Automated performance evaluation of skew-tolerant clocking schemes. International Journal of Electronics, 93 (12), 819-842.
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URI: https://hdl.handle.net/11441/77541

DOI: 10.1080/00207210500347410

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