Repositorio de producción científica de la Universidad de Sevilla

A 32, x, 32 pixel convolution processor chip for address event vision sensors with 155 ns event latency and 20 meps throughput

 

Advanced Search
 
Opened Access A 32, x, 32 pixel convolution processor chip for address event vision sensors with 155 ns event latency and 20 meps throughput
Cites

Show item statistics
Icon
Export to
Author: Camuñas Mesa, Luis Alejandro
Acosta Jiménez, Antonio José
Zamarreño Ramos, Carlos
Serrano Gotarredona, María Teresa
Linares Barranco, Bernabé
Department: Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores
Date: 2010
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers, 58 (4), 777-790.
Document type: Article
Abstract: This paper describes a convolution chip for event-driven vision sensing and processing systems. As opposed to conventional frame-constraint vision systems, in event-driven vision there is no need for frames. In frame-free event-based vision, informa...
[See more]
Cite: Camuñas Mesa, L.A., Acosta Jiménez, A.J., Zamarreño Ramos, C., Serrano Gotarredona, M.T. y Linares Barranco, B. (2010). A 32, x, 32 pixel convolution processor chip for address event vision sensors with 155 ns event latency and 20 meps throughput. IEEE Transactions on Circuits and Systems I: Regular Papers, 58 (4), 777-790.
Size: 2.629Mb
Format: PDF

URI: https://hdl.handle.net/11441/77100

DOI: 10.1109/TCSI.2010.2078851

See editor´s version

This work is under a Creative Commons License: 
Attribution-NonCommercial-NoDerivatives 4.0 Internacional

This item appears in the following Collection(s)