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Sorting networks implemented as νMOS circuits


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Author: Rodríguez Villegas, Esther
Quintana Toledo, José María
Avedillo de Juan, María José
Rueda Rueda, Adoración
Department: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Date: 1998
Published in: Electronics Letters, 34 (23), 2237-2238.
Document type: Article
Abstract: A new realisation for n-input sorters is presented. Resorting to the neuron-MOS (νMOS) concept and to an adequate electrical scheme, a compact and efficient implementation is obtained.
Cite: Rodríguez Villegas, E., Quintana Toledo, J.M., Avedillo de Juan, M.J. y Rueda Rueda, A. (1998). Sorting networks implemented as νMOS circuits. Electronics Letters, 34 (23), 2237-2238.
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DOI: 10.1049/el:19981562

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