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A 176x120 Pixel CMOS Vision Chip for Gaussian Filtering with Massivelly Parallel CDS and A/D-Conversion

 

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Opened Access A 176x120 Pixel CMOS Vision Chip for Gaussian Filtering with Massivelly Parallel CDS and A/D-Conversion
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Author: Suárez, Manuel
Brea, Víctor M.
Cabello, D.
Fernández Berni, Jorge
Carmona Galán, Ricardo
Rodríguez Vázquez, Ángel Benito
Department: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Date: 2013
Published in: European Conference on Circuit Theory and Desing (ECCTD) (2013), p 1-4
ISBN/ISSN: 978-3-00-043785-4
Document type: Presentation
Abstract: This paper conveys a proof-of-concept chip for Gaussian pyramid generation for image feature detectors. Gaussian filtering and image resizing are performed with a switchedcapacitor (SC) network. The chip is conceived as the mapping of a CMOS-3D architecture for feature detectors onto a conventional technology, with some functionality removed, and the corresponding area overhead with respect to a CMOS-3D architecture, but preserving masivelly parallel Correlated Double Sampling (CDS) and A/D conversion. The chip has been fabricated on a die of 5 5 mm2 with 0.18 m CMOS technology, achieving an array of 176 120 sensing elements (pixels). The pixels are arranged in Processing Elements (PEs). Every PE comprises four photodiodes, four SC nodes, one CDS circuit, and local circuitry for one ADC. Every PE occupies an area of 44 44 m2. The chip senses an image and computes the Gaussian pyramid with an average power consumption lower than 75 nW/pixel at 30 frames/s.
Cite: Suárez, M., Brea, V.M., Cabello, D., Fernández Berni, J., Carmona Galán, R. y Rodríguez Vázquez, Á.B. (2013). A 176x120 Pixel CMOS Vision Chip for Gaussian Filtering with Massivelly Parallel CDS and A/D-Conversion. En European Conference on Circuit Theory and Desing (ECCTD) (1-4), Dresden, Germany: Institute of Electrical and Electronics Engineers.
Size: 672.6Kb
Format: PDF

URI: https://hdl.handle.net/11441/75560

DOI: 10.1109/ECCTD.2013.6662293

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