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PCI-AER interface for Neuro-inspired Spiking Systems

 

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Opened Access PCI-AER interface for Neuro-inspired Spiking Systems
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Author: Paz Vicente, Rafael
Linares Barranco, Alejandro
Cascado Caballero, Daniel
Rodríguez Jódar, Miguel Ángel
Jiménez Moreno, Gabriel
Civit Balcells, Antón
Sevillano Ramos, José Luis
Department: Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores
Date: 2006
Published in: ISCAS 2006: IEEE International Symposium on Circuits and Systems (2006), p 3161-3164
ISBN/ISSN: 0-7803-9389-9
Document type: Presentation
Abstract: Address event representation (AER) is a neuromorphic interchip communication protocol that allows for real-time connectivity between huge number neurons located on different chips. By exploiting high speed digital communication circuits (nano-seconds), synaptic neural connections can be time multiplexed (mili-seconds). When building multi-chip muti-layered AER systems it is absolutely necessary to have a computer interface that allows: (a) to read AER interchip traffic; and (b) inject a sequence of events to the AER structure. This paper presents a PCI to AER interface, that dispatches a sequence of events with timing information. It is able to recovery the possible delays introduced by AER bus. It has been implemented in real time hardware using VHDL and tested in a PCI-AER board, developed by authors, that currently capable to send and receive events at a peak rate of 16 Mev/sec, and a typical rate of 10 Mev/sec
Cite: Paz Vicente, R., Linares Barranco, A., Cascado Caballero, D., Rodríguez Jodar, M.Á., Jiménez Moreno, G., Civit Balcells, A. y Sevillano Ramos, J.L. (2006). PCI-AER interface for Neuro-inspired Spiking Systems. En ISCAS 2006: IEEE International Symposium on Circuits and Systems (3161-3164), Island of Kos, Greece: IEEE Computer Society.
Size: 2.754Mb
Format: PDF

URI: https://hdl.handle.net/11441/74552

DOI: 10.1109/ISCAS.2006.1693296

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