Repositorio de producción científica de la Universidad de Sevilla

Complementary tunnel gate topology to reduce crosstalk effects

Opened Access Complementary tunnel gate topology to reduce crosstalk effects

Citas

buscar en

Estadísticas
Icon
Exportar a
Autor: Nuñez Martínez, Juan
Avedillo de Juan, María José
Departamento: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Fecha: 2017
Tipo de documento: Ponencia
Resumen: Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. There are design challenges associated to their distinguishing characteristic which are being addressed. In this paper the impact of the non-symmetric conduction of tunnel transistors (TFETs) on the speed of TFETs circuits under crosstalk is analyzed and a novel topology for complementary tunnel transistors gates, which mitigates the observed performance degradation without power penalties, is described and evaluated.
Tamaño: 110.5Kb
Formato: PDF

URI: https://hdl.handle.net/11441/73989

DOI: 10.1109/DCIS.2016.7845264

Ver versión del editor

Mostrar el registro completo del ítem


Esta obra está bajo una Licencia Creative Commons Atribución-NoComercial-SinDerivadas 3.0 Estados Unidos de América

Este registro aparece en las siguientes colecciones