Repositorio de producción científica de la Universidad de Sevilla

Background Digital Calibration of Comparator Offsets in Pipeline ADCs

 

Advanced Search
 
Opened Access Background Digital Calibration of Comparator Offsets in Pipeline ADCs
Cites

Show item statistics
Icon
Export to
Author: Ginés Arteaga, Antonio José
Peralías Macías, Eduardo
Rueda Rueda, Adoración
Date: 2015
Published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 99-.
Document type: Article
Abstract: This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models.
Cite: Ginés Arteaga, A.J., Peralias Macias, E. y Rueda Rueda, A. (2015). Background Digital Calibration of Comparator Offsets in Pipeline ADCs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 99-.
Size: 436.0Kb
Format: PDF

URI: http://hdl.handle.net/11441/64526

DOI: 10.1109/TVLSI.2014.2335233

See editor´s version

This work is under a Creative Commons License: 
Attribution-NonCommercial-NoDerivatives 4.0 Internacional

This item appears in the following Collection(s)