Opened Access New CMOS VLSI Linear Self-Timed Architectures

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Autor: Acosta Jiménez, Antonio José
Bellido Díaz, Manuel Jesús
Valencia Barrero, Manuel
Barriga Barros, Ángel
Jiménez, R.
Huertas Díaz, José Luis
Departamento: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Fecha: 1995
Publicado en: Second Working Conference on Asynchronous Design Methodologies (1995), p 14-23
ISBN/ISSN: 0-8186-7098-3
Tipo de documento: Ponencia
Resumen: The implementation of digital signal processor circuits via self-timed techniques is currently a valid altemative to solve some problems encountered in synchronous VLSI circuits. However; a main difference between synchronous and asynchronous circuits is the hardware resources needed to implement asynchronous circuits. This communication presents four less-costly alternatives to a previously reported linear selftimed architecture, and their application in the design of FIFO memories. Furthermore, the integration and characterization in the laboratory of prototypes of these FIFOs are presented.
Cita: Acosta, A.J., Bellido Díaz, M.J., Valencia Barrero, M., Barriga, A., Jiménez, R. y Huertas, J.L. (1995). New CMOS VLSI Linear Self-Timed Architectures. En Second Working Conference on Asynchronous Design Methodologies, London, UK.
Tamaño: 967.1Kb
Formato: PDF

URI: http://hdl.handle.net/11441/63282

DOI: 10.1109/WCADM.1995.514638

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