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Logic-Level Fast Current Simulation for Digital CMOS Circuits

 

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Opened Access Logic-Level Fast Current Simulation for Digital CMOS Circuits
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Author: Ruiz de Clavijo Vázquez, Paulino
Juan Chico, Jorge
Bellido Díaz, Manuel Jesús
Millán Calderón, Alejandro
Guerrero Martos, David
Ostúa Aranguena, Enrique
Viejo Cortés, Julián
Department: Universidad de Sevilla. Departamento de Tecnología Electrónica
Date: 2005
Published in: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728.
ISBN/ISSN: 978-3-540-29013-1
0302-9743
Document type: Chapter of Book
Abstract: Nowadays, verification of digital integrated circuit has been focused more and more from the timing and area field to current and power estimations. The main problem with this kind of verification is on the lack of precision of current estimation...
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Size: 420.8Kb
Format: PDF

URI: http://hdl.handle.net/11441/52570

DOI: 10.1007/11556930_44

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