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Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level

 

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Opened Access Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level
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Author: Baena Oliva, María del Carmen
Juan Chico, Jorge
Bellido Díaz, Manuel Jesús
Ruiz de Clavijo Vázquez, Paulino
Jiménez Fernández, Carlos Jesús
Valencia Barrero, Manuel
Department: Universidad de Sevilla. Departamento de Tecnología Electrónica
Date: 2002
Published in: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451
ISBN/ISSN: 978-3-540-44143-4
0302-9743
Document type: Chapter of Book
Abstract: Accurate estimation of switching activity is very important in digital circuits. In this paper we present a comparison between the evaluation of the switching activity calculated using logic (Verilog) and electrical (HSPICE) simulators. We also study how the variation on the delay model (min, typ, max) and parasitic effects affect the number of transitions in the circuit. Results show a variable and significant overestimation of this measurement using logic simulators even when including postlayout effects. Furthermore, we show the contribution of glitches to the overall switching activity, giving that the treatment of glitches in conventional logic simulators is the main cause of switching activity overestimation.
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URI: http://hdl.handle.net/11441/52483

DOI: 10.1007/3-540-45716-X_35

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