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Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level

 

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Opened Access Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level
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Author: Ruiz de Clavijo Vázquez, Paulino
Juan Chico, Jorge
Bellido Díaz, Manuel Jesús
Millán Calderón, Alejandro
Guerrero Martos, David
Department: Universidad de Sevilla. Departamento de Tecnología Electrónica
Date: 2002
Published in: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451
ISBN/ISSN: 978-3-540-44143-4
0302-9743
Document type: Chapter of Book
Abstract: This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current model and a current curve generation algorithm that is implemented as an attached module to a logic simulator under development called HALOTIS. The implementation is aimed at efficiency and overall estimations, making it suitable to switching noise evaluation and current peaks localisation. Simulation results and comparison to HSPICE confirm the usefulness and efficiency of the approach.
Size: 495.1Kb
Format: PDF

URI: http://hdl.handle.net/11441/52479

DOI: 10.1007/3-540-45716-X_40

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