Mostrar el registro sencillo del ítem

Ponencia

dc.creatorRuiz de Clavijo Vázquez, Paulinoes
dc.creatorJuan Chico, Jorgees
dc.creatorBellido Díaz, Manuel Jesúses
dc.creatorAcosta Jiménez, Antonio Josées
dc.creatorValencia Barrero, Manueles
dc.date.accessioned2017-01-19T10:42:52Z
dc.date.available2017-01-19T10:42:52Z
dc.date.issued2001
dc.identifier.citationRuiz de Clavijo Vázquez, P., Juan Chico, J., Bellido Díaz, M.J., Acosta Jiménez, A.J. y Valencia Barrero, M. (2001). HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. En Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001 (467-471), Munich, Germany: IEEE Computer Society.
dc.identifier.isbn0-7695-0993-2es
dc.identifier.issn1530-1591es
dc.identifier.urihttp://hdl.handle.net/11441/52463
dc.description.abstractThis communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm is intended for including the inertial and degradation delay models. Simulation results are very similar to those obtained by electrical simulators, and show a higher accuracy compared to conventional delay models implemented in current logic simulators.es
dc.description.sponsorshipMinisterio de Ciencia y Tecnología TIC 2000-1350es
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherIEEE Computer Societyes
dc.relation.ispartofDesign, Automation and Test in Europe, 2001. Conference and Exhibition 2001 (2001), p 467-471
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.titleHALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay modeles
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/submittedVersiones
dc.rights.accessrightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Tecnología Electrónicaes
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.projectIDTIC 2000-1350es
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/915065/es
dc.identifier.doi10.1109/DATE.2001.915065es
idus.format.extent5es
dc.publication.initialPage467es
dc.publication.endPage471es
dc.eventtitleDesign, Automation and Test in Europe, 2001. Conference and Exhibition 2001es
dc.eventinstitutionMunich, Germanyes
dc.relation.publicationplaceUSAes
dc.contributor.funderMinisterio de Ciencia y Tecnología (MCYT). España

FicherosTamañoFormatoVerDescripción
aafe7451ba6e5b460cf0905ca0cfa2 ...93.09KbIcon   [PDF] Ver/Abrir  

Este registro aparece en las siguientes colecciones

Mostrar el registro sencillo del ítem

Attribution-NonCommercial-NoDerivatives 4.0 Internacional
Excepto si se señala otra cosa, la licencia del ítem se describe como: Attribution-NonCommercial-NoDerivatives 4.0 Internacional