Repositorio de producción científica de la Universidad de Sevilla

Degradation Delay Model Extension to CMOS Gates

 

Advanced Search
 
Opened Access Degradation Delay Model Extension to CMOS Gates
Cites

Show item statistics
Icon
Export to
Author: Juan Chico, Jorge
Bellido Díaz, Manuel Jesús
Ruiz de Clavijo Vázquez, Paulino
Acosta Jiménez, Antonio José
Valencia Barrero, Manuel
Department: Universidad de Sevilla. Departamento de Tecnología Electrónica
Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Date: 2000
Published in: Integrated Circuit Design. PATMOS 2000. Lecture Notes in Computer Science, vol 1918
ISBN/ISSN: 978-3-540-41068-3
0302-9743
Document type: Chapter of Book
Abstract: This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic gates. A gate-level approach is followed. At a first stage, all input collisions producing degradation are studied and classified. Then, an exhaustive model is proposed, which defines a set of parameters for each particular collision. This way, a full and accurate description of the degradation effect is obtained (compared to HSPICE) at the cost of storing a rather high number of parameters. To solve that, a simplified model is also proposed maintaining similar accuracy but with a reduced number of parameters and a simplified characterization process. Finally, the complexity of both models is compared.
Size: 354.5Kb
Format: PDF

URI: http://hdl.handle.net/11441/52449

DOI: 10.1007/3-540-45373-3_15

See editor´s version

This work is under a Creative Commons License: 
Attribution-NonCommercial-NoDerivatives 4.0 Internacional

This item appears in the following Collection(s)