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A 74dB dynamic range, 1.1-mhz signal band 4th-order 2-1-1 cascade multi-bit CMOS ΣΔ modulator for ADSL

 

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Opened Access A 74dB dynamic range, 1.1-mhz signal band 4th-order 2-1-1 cascade multi-bit CMOS ΣΔ modulator for ADSL
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Author: Medeiro Hidalgo, Fernando
Pérez Verdú, Belén
Rodríguez Vázquez, Ángel Benito
Department: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Date: 1997
Published in: European Solid-State Circuits Conference (ESSCIRC’97), pp. 72-75, Southampton - UK, September 16-18
Document type: Presentation
Abstract: This paper explores the use of ΣΔ techniques for A/D conversion exceeding 1-MHz signal bandwidth. A cascade modulator architecture is proposed which combines single-bit and multi-bit quantization to obtain more than 12-b Dynamic Range (DR) with an oversampling ratio of only 16, and with neither calibration nor trimming required. Measurements from a 0.7mm CMOS prototype show 74dB DR in 1.1-MHz signal band at 35.7-MHz clock rate, with a power consumption of 55mW from a 5-V supply.
Size: 2.525Mb
Format: PDF

URI: http://hdl.handle.net/11441/33646

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