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High-order cascade multi-bit Σ∆ modulators for high-speed A/D conversion

 

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Opened Access High-order cascade multi-bit Σ∆ modulators for high-speed A/D conversion
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Author: Río Fernández, Rocío del
Medeiro Hidalgo, Fernando
Pérez Verdú, Belén
Rodríguez Vázquez, Ángel Benito
Department: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Date: 1998
Published in: Design of Circuits and Integrated Systems Conference (13ª. 1998. Madrid, España), 76-81
ISBN/ISSN: 8460683457
Document type: Presentation
Abstract: The use of Sigma-Delta (Σ∆) modulation for analog-to-digital conversion (ADC) in the communication frequency range is evaluated. Two high-order multi-bit architectures are proposed to achieve +12-bit dynamic range at 4Msample/s Nyquist rate using very low oversampling ratio. They show very low sensitivity to the internal D-to-A conversion (DAC) error with no calibration required. Simulations show that such performance can be achieved even in presence of circuit imperfections
Size: 4.300Mb
Format: PDF

URI: http://hdl.handle.net/11441/33140

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