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Signal Sampling Based Transition Modeling for Digital Gates Characterization

 

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Author: Millán Calderón, Alejandro
Juan Chico, Jorge
Bellido Díaz, Jorge
Ruiz de Clavijo Vázquez, Paulino
Guerrero Martos, David
Ostúa Aranguena, Enrique
Department: Universidad de Sevilla. Departamento de Tecnología Electrónica
Date: 2004
Published in: Lecture Notes in Computer Science, 3254, 829-837.
Document type: Article
Abstract: Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel method to drive the timing characterization of logic gates under variable input transition times. The method is based on sampling and scaling realistic transition waveforms and it is easy to implement and introduces negligible computational overhead in the characterization process. We show how models characterized using the proposed method may improve accuracy from 5% to 8%.
Cite: Millán Calderón, A., Juan Chico, J., Bellido Díaz, J., Ruiz de Clavijo Vázquez, P., Guerrero Martos, D. y Ostúa Aranguena, E. (2004). Signal Sampling Based Transition Modeling for Digital Gates Characterization. Lecture Notes in Computer Science, 3254, 829-837.
Size: 140.9Kb
Format: PDF

URI: http://hdl.handle.net/11441/31227

DOI: 10.1007/978-3-540-30205-6_85

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