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RAISE: A detailed routing algorithm for field-programmable gate arrays

Opened Access RAISE: A detailed routing algorithm for field-programmable gate arrays
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Autor: Baena Lecuyer, Vicente
Aguirre Echanove, Miguel Ángel
Torralba Silgado, Antonio Jesús
García Franquelo, Leopoldo
Faura, J.
Departamento: Universidad de Sevilla. Departamento de Ingeniería Electrónica
Fecha: 1997
Publicado en: Design of Circuits and Integrated Systems Conference. Sevilla, España : DCIS
Tipo de documento: Ponencia
Resumen: This paper describes a new detailed routing algorithm, speciffically designed for those types of architecturesthat are found on the most recent generations of Field-Programmable Gate Arrays (FP-GAs). The algorithm, called RAISE, can be applied to a broad range of optimizations problems and has been used for detailed routing of symmetrical FPGAs, whose routing architecture consists of rows and columns of logic cells interconnected by routing channels. RAISE (Router using AadaptIve Simulated Evolution) searches not only for a possible solution, but tries to find the one with minimum delay. Excelent routing results have been obtained over a set of several benchmark circuits getting solutions close to the minimum number of tracks.
Tamaño: 49.78Kb
Formato: PDF


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