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Design of a band-pass sigma-delta modulator with reduced number of opamps
dc.creator | Pérez Vega-Leal, Alfredo | es |
dc.creator | Muñoz Chavero, Fernando | es |
dc.creator | González Carvajal, Ramón | es |
dc.creator | Torralba Silgado, Antonio Jesús | es |
dc.creator | Tombs, J. N. | |
dc.creator | García Franquelo, Leopoldo | es |
dc.date.accessioned | 2015-03-26T08:28:24Z | |
dc.date.available | 2015-03-26T08:28:24Z | |
dc.date.issued | 2000 | es |
dc.identifier.uri | http://hdl.handle.net/11441/23557 | |
dc.description.abstract | This paper is intended to compare the performance of a Band-Pass converter structure and its Low-Pass prototype 2nd order Sigma-Delta Analog to Digital converter. For this purpose Matlab simulations for the 4th order Band-Pass converter have been performed and its power consumption calculated when using the equivalent Op-Amp used m the Low-Pass modulator. First of all will be described the method used to calculate the transfer function and, thus the structure of the Band-Pass structure to be tested. After a band-pass transfer function has been obtained it is implemented using reduced number of opamps. This topology is compared to the existing ones and a system level simulation and characterisation is performed. Finally, jitter limitations are studied. Transistor level simulations using Spectre have been done in order to validate MATLAB simulations prior to layout design. | en |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.relation.ispartof | Design of Circuits and Integrated Systems, 156-161. Montpellier, Francia : DCIS | en |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | es |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | es |
dc.title | Design of a band-pass sigma-delta modulator with reduced number of opamps | en |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Ingeniería Electrónica | es |
dc.relation.publisherversion | 10.13140/2.1.3222.6246 | |
dc.identifier.idus | https://idus.us.es/xmlui/handle/11441/23557 |
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