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Patente
Método para análisis y test funcional de circuito digitales de gran dimensión mediante emuladores hardware.
(Oficina Española de Patentes y Marcas , 2003-06-16)
Método para análisis y test funcional de circuito digitales de gran dimensión mediante emuladores HARDWARE.Parte de un número indefinido de eventos o condiciones (1), (1')... (1n ), respectivos circuitos detectores (2), ...
Ponencia
OFDM synchronization scheme for Power Line Telecommunications (PLT)
(2001)
This paper presents a new scheme for OFDM time and frequency synchronization with application in Power Line Telecommunications (PLT). Simulation results show an excellent behavior, even for the low values of SNR in the ...
Ponencia
HADES-1: A rapid prototyping environment based on advanced FPGA’s
(2001)
Rapid prototyping of large digital systems is becoming supported with the use of new advanced FPGA's. These FPGA's can give more Information than functional simulation and emulation tasks, due to their inner inspection ...
Artículo
Selective Harmonic Mitigation Technique for High-Power Converters
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
In high-power applications, the maximum switching frequency is limited due to thermal losses. This leads to highly distorted output waveforms. In such applications, it is necessary to filter the output waveforms using bulky ...
Ponencia
Radiation environment emulation for VLSI designs: a low cost platform based on xilinx FPGA's
(IEEE, 2007)
As technology shrinks, critical industral applications have to be designed with special care. VLSI circuits become more sensitive to ambient radiation: it affects to the internal structures, combinational or sequential ...
Ponencia
RAISE: A detailed routing algorithm for field-programmable gate arrays
(1997)
This paper describes a new detailed routing algorithm, speciffically designed for those types of architecturesthat are found on the most recent generations of Field-Programmable Gate Arrays (FP-GAs). The algorithm, called ...
Ponencia
Digital test design with an "ad hoc" strategy for an industrial ASIC with large dimension
(1996)
The development of digital ASIC's with a large area states a lot of doubts when the ingenieer must design a test strategy. The design of an industrial circuit advises a test to be made quite similar to the normal field ...
Ponencia
Aceleración de un algoritmo de enfriamiento simulado mediante particionamiento de redes. Aplicación a "placement" de circuitos VLSI
(1995)
Se propone un nuevo método de mejora de los resultados del "placement" de un circuito VLSI. El método propuesto utiliza un particionamiento recursivo para obtener una solución de partida para el posterior proceso de ...